260 lines
8.1 KiB
C
260 lines
8.1 KiB
C
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/*
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* Hardware-specific External Interface I/O core definitions
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* for the BCM47xx family of SiliconBackplane-based chips.
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*
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* The External Interface core supports a total of three external chip selects
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* supporting external interfaces. One of the external chip selects is
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* used for Flash, one is used for PCMCIA, and the other may be
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* programmed to support either a synchronous interface or an
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* asynchronous interface. The asynchronous interface can be used to
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* support external devices such as UARTs and the BCM2019 Bluetooth
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* baseband processor.
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* The external interface core also contains 2 on-chip 16550 UARTs, clock
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* frequency control, a watchdog interrupt timer, and a GPIO interface.
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, Michael Buesch
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*
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* Licensed under the GPL version 2. See COPYING for details.
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*/
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#ifndef LINUX_SSB_EXTIFCORE_H_
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#define LINUX_SSB_EXTIFCORE_H_
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/* external interface address space */
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#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x)
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#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
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#define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
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#define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
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#define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
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#define SSB_EXTIF_NR_GPIOOUT 5
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/* GPIO NOTE:
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* The multiple instances of output and output enable registers
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* are present to allow driver software for multiple cores to control
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* gpio outputs without needing to share a single register pair.
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* Use the following helper macro to get a register offset value.
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*/
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#define SSB_EXTIF_GPIO_OUT(index) ({ \
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BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
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SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \
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})
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#define SSB_EXTIF_GPIO_OUTEN(index) ({ \
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BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
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SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \
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})
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/** EXTIF core registers **/
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#define SSB_EXTIF_CTL 0x0000
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#define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
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#define SSB_EXTIF_EXTSTAT 0x0004
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#define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
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#define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */
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#define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */
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#define SSB_EXTIF_PCMCIA_CFG 0x0010
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#define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
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#define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018
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#define SSB_EXTIF_PCMCIA_IOWAIT 0x001C
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#define SSB_EXTIF_PROG_CFG 0x0020
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#define SSB_EXTIF_PROG_WAITCNT 0x0024
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#define SSB_EXTIF_FLASH_CFG 0x0028
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#define SSB_EXTIF_FLASH_WAITCNT 0x002C
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#define SSB_EXTIF_WATCHDOG 0x0040
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#define SSB_EXTIF_CLOCK_N 0x0044
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#define SSB_EXTIF_CLOCK_SB 0x0048
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#define SSB_EXTIF_CLOCK_PCI 0x004C
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#define SSB_EXTIF_CLOCK_MII 0x0050
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#define SSB_EXTIF_GPIO_IN 0x0060
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#define SSB_EXTIF_GPIO_OUT_BASE 0x0064
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#define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068
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#define SSB_EXTIF_EJTAG_OUTEN 0x0090
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#define SSB_EXTIF_GPIO_INTPOL 0x0094
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#define SSB_EXTIF_GPIO_INTMASK 0x0098
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#define SSB_EXTIF_UART_DATA 0x0300
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#define SSB_EXTIF_UART_TIMER 0x0310
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#define SSB_EXTIF_UART_FCR 0x0320
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#define SSB_EXTIF_UART_LCR 0x0330
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#define SSB_EXTIF_UART_MCR 0x0340
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#define SSB_EXTIF_UART_LSR 0x0350
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#define SSB_EXTIF_UART_MSR 0x0360
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#define SSB_EXTIF_UART_SCRATCH 0x0370
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/* pcmcia/prog/flash_config */
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#define SSB_EXTCFG_EN (1 << 0) /* enable */
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#define SSB_EXTCFG_MODE 0xE /* mode */
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#define SSB_EXTCFG_MODE_SHIFT 1
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#define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */
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#define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */
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#define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */
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#define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */
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#define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */
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#define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */
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#define SSB_EXTCFG_CLKDIV_SHIFT 6
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#define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */
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#define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */
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#define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */
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#define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */
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#define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */
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/* pcmcia_memwait */
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#define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */
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#define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */
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#define SSB_PCMCIA_MEMW_1_SHIFT 8
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#define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */
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#define SSB_PCMCIA_MEMW_2_SHIFT 16
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#define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */
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#define SSB_PCMCIA_MEMW_3_SHIFT 24
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/* pcmcia_attrwait */
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#define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */
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#define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */
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#define SSB_PCMCIA_ATTW_1_SHIFT 8
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#define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */
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#define SSB_PCMCIA_ATTW_2_SHIFT 16
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#define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */
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#define SSB_PCMCIA_ATTW_3_SHIFT 24
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/* pcmcia_iowait */
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#define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */
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#define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */
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#define SSB_PCMCIA_IOW_1_SHIFT 8
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#define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */
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#define SSB_PCMCIA_IOW_2_SHIFT 16
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#define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */
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#define SSB_PCMCIA_IOW_3_SHIFT 24
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/* prog_waitcount */
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#define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */
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#define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */
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#define SSB_PROG_WCNT_1_SHIFT 8
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#define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */
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#define SSB_PROG_WCNT_2_SHIFT 16
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#define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */
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#define SSB_PROG_WCNT_3_SHIFT 24
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#define SSB_PROG_W0 0x0000000C
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#define SSB_PROG_W1 0x00000A00
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#define SSB_PROG_W2 0x00020000
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#define SSB_PROG_W3 0x01000000
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/* flash_waitcount */
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#define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */
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#define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */
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#define SSB_FLASH_WCNT_1_SHIFT 8
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#define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */
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#define SSB_FLASH_WCNT_2_SHIFT 16
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#define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */
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#define SSB_FLASH_WCNT_3_SHIFT 24
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/* watchdog */
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#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
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#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
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#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
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/ (SSB_EXTIF_WATCHDOG_CLK / 1000))
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#ifdef CONFIG_SSB_DRIVER_EXTIF
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struct ssb_extif {
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struct ssb_device *dev;
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spinlock_t gpio_lock;
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};
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static inline bool ssb_extif_available(struct ssb_extif *extif)
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{
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return (extif->dev != NULL);
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}
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extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
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u32 *plltype, u32 *n, u32 *m);
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extern void ssb_extif_timing_init(struct ssb_extif *extif,
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unsigned long ns);
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extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
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/* Extif GPIO pin access */
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u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
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u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
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u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
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u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
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u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
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#ifdef CONFIG_SSB_SERIAL
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extern int ssb_extif_serial_init(struct ssb_extif *extif,
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struct ssb_serial_port *ports);
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#endif /* CONFIG_SSB_SERIAL */
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#else /* CONFIG_SSB_DRIVER_EXTIF */
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/* extif disabled */
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struct ssb_extif {
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};
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static inline bool ssb_extif_available(struct ssb_extif *extif)
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{
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return 0;
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}
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static inline
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void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
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u32 *plltype, u32 *n, u32 *m)
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{
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}
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static inline
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void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
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{
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}
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static inline
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u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
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{
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return 0;
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}
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static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
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{
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return 0;
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}
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static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
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u32 value)
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{
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return 0;
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}
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static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
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u32 value)
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{
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return 0;
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}
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static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
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u32 value)
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{
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return 0;
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}
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static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
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u32 value)
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{
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return 0;
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}
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#ifdef CONFIG_SSB_SERIAL
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static inline int ssb_extif_serial_init(struct ssb_extif *extif,
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struct ssb_serial_port *ports)
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{
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return 0;
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}
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#endif /* CONFIG_SSB_SERIAL */
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#endif /* CONFIG_SSB_DRIVER_EXTIF */
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#endif /* LINUX_SSB_EXTIFCORE_H_ */
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