369 lines
11 KiB
C
369 lines
11 KiB
C
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/*
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* Copyright (c) 2010 Google, Inc
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* Copyright (c) 2014-2020, NVIDIA Corporation. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SOC_TEGRA_PMC_H__
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#define __SOC_TEGRA_PMC_H__
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#include <linux/reboot.h>
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#include <linux/usb/ch9.h>
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#include <soc/tegra/pm.h>
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struct clk;
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struct reset_control;
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#ifdef CONFIG_PM_SLEEP
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
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void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
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void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
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#endif /* CONFIG_PM_SLEEP */
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#ifdef CONFIG_SMP
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bool tegra_pmc_cpu_is_powered(int cpuid);
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int tegra_pmc_cpu_power_on(int cpuid);
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int tegra_pmc_cpu_remove_clamping(int cpuid);
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#endif /* CONFIG_SMP */
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/*
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* powergate and I/O rail APIs
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*/
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#ifndef CONFIG_TEGRA_POWERGATE
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#define TEGRA_POWERGATE_CPU 0
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#define TEGRA_POWERGATE_3D 1
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#define TEGRA_POWERGATE_VENC 2
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#define TEGRA_POWERGATE_PCIE 3
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#define TEGRA_POWERGATE_VDEC 4
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#define TEGRA_POWERGATE_L2 5
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#define TEGRA_POWERGATE_MPE 6
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#define TEGRA_POWERGATE_HEG 7
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#define TEGRA_POWERGATE_SATA 8
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#define TEGRA_POWERGATE_CPU1 9
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#define TEGRA_POWERGATE_CPU2 10
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#define TEGRA_POWERGATE_CPU3 11
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#define TEGRA_POWERGATE_CELP 12
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#define TEGRA_POWERGATE_3D1 13
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#define TEGRA_POWERGATE_CPU0 14
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#define TEGRA_POWERGATE_C0NC 15
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#define TEGRA_POWERGATE_C1NC 16
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#define TEGRA_POWERGATE_SOR 17
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#define TEGRA_POWERGATE_DIS 18
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#define TEGRA_POWERGATE_DISB 19
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#define TEGRA_POWERGATE_XUSBA 20
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#define TEGRA_POWERGATE_XUSBB 21
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#define TEGRA_POWERGATE_XUSBC 22
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#define TEGRA_POWERGATE_VIC 23
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#define TEGRA_POWERGATE_IRAM 24
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#define TEGRA_POWERGATE_NVDEC 25
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#define TEGRA_POWERGATE_NVJPG 26
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#define TEGRA_POWERGATE_AUD 27
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#define TEGRA_POWERGATE_DFD 28
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#define TEGRA_POWERGATE_VE2 29
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#endif
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#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
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#define TEGRA_IO_RAIL_CSIA 0
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#define TEGRA_IO_RAIL_CSIB 1
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#define TEGRA_IO_RAIL_DSI 2
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#define TEGRA_IO_RAIL_MIPI_BIAS 3
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#define TEGRA_IO_RAIL_PEX_BIAS 4
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#define TEGRA_IO_RAIL_PEX_CLK1 5
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#define TEGRA_IO_RAIL_PEX_CLK2 6
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#define TEGRA_IO_RAIL_USB0 9
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#define TEGRA_IO_RAIL_USB1 10
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#define TEGRA_IO_RAIL_USB2 11
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#define TEGRA_IO_RAIL_USB_BIAS 12
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#define TEGRA_IO_RAIL_NAND 13
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#define TEGRA_IO_RAIL_UART 14
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#define TEGRA_IO_RAIL_BB 15
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#define TEGRA_IO_RAIL_AUDIO 17
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#define TEGRA_IO_RAIL_HSIC 19
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#define TEGRA_IO_RAIL_COMP 22
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#define TEGRA_IO_RAIL_HDMI 28
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#define TEGRA_IO_RAIL_PEX_CNTRL 32
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#define TEGRA_IO_RAIL_SDMMC1 33
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#define TEGRA_IO_RAIL_SDMMC3 34
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#define TEGRA_IO_RAIL_SDMMC4 35
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#define TEGRA_IO_RAIL_CAM 36
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#define TEGRA_IO_RAIL_RES 37
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#define TEGRA_IO_RAIL_HV 38
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#define TEGRA_IO_RAIL_DSIB 39
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#define TEGRA_IO_RAIL_DSIC 40
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#define TEGRA_IO_RAIL_DSID 41
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#define TEGRA_IO_RAIL_CSIE 44
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#define TEGRA_IO_RAIL_LVDS 57
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#define TEGRA_IO_RAIL_SYS_DDC 58
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/* Define reboot-reset mode */
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#define RECOVERY_MODE BIT(31)
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#define BOOTLOADER_MODE BIT(30)
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#define UPDATE_MODE BIT(29)
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#define FORCED_RECOVERY_MODE BIT(1)
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#ifndef CONFIG_TEGRA_POWERGATE
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#if defined CONFIG_ARCH_TEGRA
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int tegra_powergate_is_powered(int id);
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int tegra_powergate_power_on(int id);
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int tegra_powergate_power_off(int id);
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int tegra_powergate_remove_clamping(int id);
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(int id, struct clk *clk,
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struct reset_control *rst);
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#else
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static inline int tegra_powergate_is_powered(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_power_on(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_power_off(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_remove_clamping(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
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struct reset_control *rst)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_ARCH_TEGRA */
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#endif /* CONFIG_TEGRA_POWERGATE */
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enum tegra_system_reset_reason {
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TEGRA_POWER_ON_RESET, /* 0 */
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TEGRA_AO_WATCHDOG, /* 1 */
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TEGRA_DENVER_WATCHDOG, /* 2 */
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TEGRA_BPMP_WATCHDOG, /* 3 */
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TEGRA_SCE_WATCHDOG, /* 4 */
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TEGRA_SPE_WATCHDOG, /* 5 */
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TEGRA_APE_WATCHDOG, /* 6 */
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TEGRA_A57_WATCHDOG, /* 7 */
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TEGRA_SENSOR, /* 8 */
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TEGRA_AOTAG, /* 9 */
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TEGRA_VFSENSOR, /* 10 */
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TEGRA_SOFTWARE_RESET, /* 11 */
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TEGRA_SC7, /* 12 */
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TEGRA_HSM, /* 13 */
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TEGRA_CSITE, /* 14 */
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TEGRA_WATCHDOG, /* 15, T210 */
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TEGRA_LP0, /* 16, T210 */
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PMIC_WATCHDOG_POR, /* 17 */
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TEGRA_RESET_REASON_MAX
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};
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enum tegra_system_reset_level {
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TEGRA_RESET_LEVEL_L0,
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TEGRA_RESET_LEVEL_L1,
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TEGRA_RESET_LEVEL_L2,
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TEGRA_RESET_LEVEL_MAX
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};
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int tegra_pmc_set_reboot_reason(u32 reboot_reason);
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int tegra_pmc_clear_reboot_reason(u32 reboot_reason);
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void tegra_pmc_write_bootrom_command(u32 command_offset, unsigned long val);
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void tegra_pmc_reset_system(void);
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enum tegra_system_reset_reason tegra_pmc_get_system_reset_reason(void);
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enum tegra_system_reset_level tegra_pmc_get_system_reset_level(void);
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#if defined(CONFIG_ARCH_TEGRA) && !defined(CONFIG_TEGRA186_PMC)
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void tegra_pmc_io_dpd_clear(void);
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int tegra_pmc_io_pad_low_power_enable(const char *pad_name);
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int tegra_pmc_io_pad_low_power_disable(const char *pad_name);
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int tegra_io_rail_power_on(int id);
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int tegra_io_rail_power_off(int id);
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int tegra_pmc_io_pad_set_voltage(const char *pad_name, unsigned int pad_uv);
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int tegra_pmc_io_pad_get_voltage(const char *pad_name);
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#else
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static inline void tegra_pmc_io_dpd_clear(void)
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{
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}
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static inline int tegra_pmc_io_pad_low_power_enable(const char *pad_name)
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{
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return 0;
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}
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static inline int tegra_pmc_io_pad_low_power_disable(const char *pad_name)
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{
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return 0;
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}
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static inline int tegra_io_rail_power_on(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_rail_power_off(int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_pmc_io_pad_set_voltage(const char *pad_name,
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unsigned int pad_uv)
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{
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return -ENOSYS;
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}
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static inline int tegra_pmc_io_pad_get_voltage(const char *pad_name)
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{
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return -ENOSYS;
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}
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#endif
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int tegra_pmc_pwm_blink_enable(void);
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int tegra_pmc_pwm_blink_disable(void);
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int tegra_pmc_pwm_blink_config(int duty_ns, int period_ns);
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int tegra_pmc_soft_led_blink_enable(void);
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int tegra_pmc_soft_led_blink_disable(void);
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int tegra_pmc_soft_led_blink_configure(int duty_cycle_ns, int ll_period_ns,
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int ramp_time_ns);
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int tegra_pmc_soft_led_blink_set_ramptime(int ramp_time_ns);
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int tegra_pmc_soft_led_blink_set_short_period(int short_low_period_ns);
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/* T210 USB2 SLEEPWALK APIs */
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struct tegra_utmi_pad_config {
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u32 tctrl;
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u32 pctrl;
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u32 rpd_ctrl;
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};
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int tegra_pmc_utmi_phy_enable_sleepwalk(int port, enum usb_device_speed speed,
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struct tegra_utmi_pad_config *config);
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int tegra_pmc_utmi_phy_disable_sleepwalk(int port);
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int tegra_pmc_hsic_phy_enable_sleepwalk(int port);
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int tegra_pmc_hsic_phy_disable_sleepwalk(int port);
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void tegra_pmc_fuse_control_ps18_latch_set(void);
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void tegra_pmc_fuse_control_ps18_latch_clear(void);
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void tegra_pmc_fuse_disable_mirroring(void);
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void tegra_pmc_fuse_enable_mirroring(void);
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bool tegra_pmc_fuse_is_redirection_enabled(void);
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/* Legacy APIs for IO DPD enable/disable */
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/* Tegra io dpd entry - for each supported driver */
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struct tegra_io_dpd {
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const char *name; /* driver name */
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u8 io_dpd_reg_index; /* io dpd register index */
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u8 io_dpd_bit; /* bit position for driver in dpd register */
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};
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static inline void tegra_io_dpd_enable(struct tegra_io_dpd *hnd)
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{
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tegra_pmc_io_pad_low_power_enable(hnd->name);
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}
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static inline void tegra_io_dpd_disable(struct tegra_io_dpd *hnd)
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{
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tegra_pmc_io_pad_low_power_disable(hnd->name);
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}
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/**
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* struct tegra_thermtrip_pmic_data - PMIC shutdown command data
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* @poweroff_reg_data: The data to write to turn the system off
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* @poweroff_reg_addr: The PMU address of poweroff register
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* @reset_tegra: Flag indicating whether or not the system
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* will shutdown during a thermal trip.
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* @controller_type: If this field is set to 0, the PMIC is
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* connected via I2C. If it is set to 1,
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* it is connected via SPI. If it is set to
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* 2, it is connected via GPIO.
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* @i2c_controller_id: The i2c bus controller id
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* @pinmux: An array index used to configure which pins
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* on the chip are muxed to the I2C/SPI/GPIO
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* controller that is in use. Contact NVIDIA
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* for more information on what these index values
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* mean for a given chip.
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* @pmu_16bit_ops: If 0, sends three bytes from the PMC_SCRATCH54
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* register to the PMIC to turn it off; if 1, sends
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* four bytes from the PMC_SCRATCH54 register to the PMIC
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* to turn it off, plus one other byte. Must be set to
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* 0 - the current code does not support 16 bit
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* operations.
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* @pmu_i2c_addr: The address of the PMIC on the I2C bus
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*
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* When the SoC temperature gets too high, the SOC_THERM hardware can
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* reset the SoC, and, by setting a bit in one of its registers, can
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* instruct the boot ROM to power off the Tegra SoC. This data
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* structure contains the information that the boot ROM needs to tell
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* the PMIC to shut down.
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*
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* @poweroff_reg_data and @poweroff_reg_addr are written to the PMC SCRATCH54
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* register.
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*
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* @reset_tegra, @controller_type, @i2c_controller_id, @pinmux, @pmu_16bit_ops
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* and @pmu_i2c_addr are written to the PMC SCRATCH55 register.
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*/
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struct tegra_thermtrip_pmic_data {
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u8 poweroff_reg_data;
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u8 poweroff_reg_addr;
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u8 reset_tegra;
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u8 controller_type;
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u8 i2c_controller_id;
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u8 pinmux;
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u8 pmu_16bit_ops;
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u8 pmu_i2c_addr;
|
||
|
|
};
|
||
|
|
|
||
|
|
void tegra_pmc_config_thermal_trip(struct tegra_thermtrip_pmic_data *data);
|
||
|
|
void tegra_pmc_enable_thermal_trip(void);
|
||
|
|
void tegra_pmc_lock_thermal_shutdown(void);
|
||
|
|
|
||
|
|
#if defined(CONFIG_PADCTRL_GENERIC_TEGRA_IO_PAD)
|
||
|
|
int tegra_io_pads_padctrl_init(struct device *dev);
|
||
|
|
#else
|
||
|
|
static inline int tegra_io_pads_padctrl_init(struct device *dev)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void tegra_pmc_ufs_pwrcntrl_update(unsigned long mask, unsigned long val);
|
||
|
|
unsigned long tegra_pmc_ufs_pwrcntrl_get(void);
|
||
|
|
|
||
|
|
int tegra_pmc_nvcsi_brick_getstatus(const char *pad_name);
|
||
|
|
int tegra_pmc_nvcsi_ab_brick_dpd_enable(void);
|
||
|
|
int tegra_pmc_nvcsi_cdef_brick_dpd_enable(void);
|
||
|
|
int tegra_pmc_nvcsi_ab_brick_dpd_disable(void);
|
||
|
|
int tegra_pmc_nvcsi_cdef_brick_dpd_disable(void);
|
||
|
|
|
||
|
|
bool tegra_pmc_is_halt_in_fiq(void);
|
||
|
|
void tegra_pmc_sata_pwrgt_update(unsigned long mask,
|
||
|
|
unsigned long val);
|
||
|
|
unsigned long tegra_pmc_sata_pwrgt_get(void);
|
||
|
|
int tegra_pmc_save_se_context_buffer_address(u32 add);
|
||
|
|
u32 tegra_pmc_get_se_context_buffer_address(void);
|
||
|
|
void tegra_pmc_writel_relaxed(u32 value, unsigned long offset);
|
||
|
|
u32 tegra_pmc_readl(unsigned long offset);
|
||
|
|
void tegra_pmc_writel(u32 value, unsigned long offset);
|
||
|
|
|
||
|
|
#endif /* __SOC_TEGRA_PMC_H__ */
|