388 lines
18 KiB
C
388 lines
18 KiB
C
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/*
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* Copyright 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef DRM_FOURCC_H
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#define DRM_FOURCC_H
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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/* color index */
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#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
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/* 8 bpp Red */
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#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
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/* 16 bpp RG */
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#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
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#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
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/* 8 bpp RGB */
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#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
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#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
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/* 16 bpp RGB */
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#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
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#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
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#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
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#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
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#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
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#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
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#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
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#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
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#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
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#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
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#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
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#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
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#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
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#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
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#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
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#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
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#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
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#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
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/* 24 bpp RGB */
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#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
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#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
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/* 32 bpp RGB */
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#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
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#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
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#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
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#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
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#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
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#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
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#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
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#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
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#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
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#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
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#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
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#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
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#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
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#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
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#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
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#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
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/* packed YCbCr */
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#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
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#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
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#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
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#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [7:0] Y
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* index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
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* or
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* index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
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*/
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#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
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#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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* index 1: Cb plane, [7:0] Cb
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* index 2: Cr plane, [7:0] Cr
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* or
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* index 1: Cr plane, [7:0] Cr
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* index 2: Cb plane, [7:0] Cb
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*/
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#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
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#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
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#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
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#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
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#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
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/*
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* Format Modifiers:
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*
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* Format modifiers describe, typically, a re-ordering or modification
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* of the data in a plane of an FB. This can be used to express tiled/
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* swizzled formats, or compression, or a combination of the two.
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*
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* The upper 8 bits of the format modifier are a vendor-id as assigned
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* below. The lower 56 bits are assigned as vendor sees fit.
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*/
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
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#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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/* add more to the end as needed */
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/* For backward compatibility */
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#define DRM_FORMAT_MOD_VENDOR_NV 0x03
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#define fourcc_mod_code(vendor, val) \
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((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
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/*
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* Format Modifier tokens:
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*
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* When adding a new token please document the layout with a code comment,
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* similar to the fourcc codes above. drm_fourcc.h is considered the
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* authoritative source for all of these.
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*/
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/* Intel framebuffer modifiers */
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/*
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* Intel X-tiling layout
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*
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* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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* in row-major layout. Within the tile bytes are laid out row-major, with
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* a platform-dependent stride. On top of that the memory can apply
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* platform-depending swizzling of some higher address bits into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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*/
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#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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/*
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* Intel Y-tiling layout
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*
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* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
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* chunks column-major, with a platform-dependent height. On top of that the
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* memory can apply platform-depending swizzling of some higher address bits
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* into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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*/
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#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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/*
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* Intel Yf-tiling layout
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*
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* This is a tiled layout using 4Kb tiles in row-major layout.
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* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
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* are arranged in four groups (two wide, two high) with column-major layout.
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* Each group therefore consits out of four 256 byte units, which are also laid
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* out as 2x2 column-major.
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* 256 byte units are made out of four 64 byte blocks of pixels, producing
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* either a square block or a 2:1 unit.
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* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
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* in pixel depends on the pixel depth.
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*/
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#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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* Macroblocks are laid in a Z-shape, and each pixel data is following the
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* standard NV12 style.
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* As for NV12, an image is the result of two frame buffers: one for Y,
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* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
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* Alignment requirements are (for each buffer):
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* - multiple of 128 pixels for the width
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* - multiple of 32 pixels for the height
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*
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* For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/*
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* Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
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* and Tegra GPUs starting with Tegra K1.
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*
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* Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
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* based on the architecture generation. GOBs themselves are then arranged in
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* 3D blocks, with the block dimensions (in terms of GOBs) always being a power
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* of two, and hence expressible as their log2 equivalent (E.g., "2" represents
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* a block depth or height of "4").
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*
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* Macro
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* Bits Param Description
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* ---- ----- -----------------------------------------------------------------
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*
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* 3:0 h log2(height) of each block, in GOBs. Placed here for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 4:4 - Must be 1, to indicate block-linear layout. Necessary for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
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* size). Must be zero.
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*
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* Note there is no log2(width) parameter. Some portions of the
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* hardware support a block width of two gobs, but it is impractical
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* to use due to lack of support elsewhere, and has no known
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* benefits.
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*
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* 11:9 - Reserved (To support 2D-array textures with variable array stride
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* in blocks, specified via log2(tile width in blocks)). Must be
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* zero.
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*
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* 19:12 k Page Kind. This value directly maps to a field in the page
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* tables of all GPUs >= NV50. It affects the exact layout of bits
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* in memory and can be derived from the tuple
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*
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* (format, GPU model, compression type, samples per pixel)
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*
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* Where compression type is defined below. If GPU model were
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* implied by the format modifier, format, or memory buffer, page
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* kind would not need to be included in the modifier itself, but
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* since the modifier should define the layout of the associated
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* memory buffer independent from any device or other context, it
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* must be included here.
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*
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* 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
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* starting with Fermi GPUs. Additionally, the mapping between page
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* kind and bit layout has changed at various points.
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*
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* 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
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* 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
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* 2 = Gob Height 8, Turing+ Page Kind mapping
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* 3 = Reserved for future use.
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*
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* 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
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* bit remapping step that occurs at an even lower level than the
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* page kind and block linear swizzles. This causes the layout of
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* surfaces mapped in those SOC's GPUs to be incompatible with the
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* equivalent mapping on other GPUs in the same system.
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*
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* 0 = Tegra K1 - Tegra Parker/TX2 Layout.
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* 1 = Desktop GPU and Tegra Xavier+ Layout
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*
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* 25:23 c Lossless Framebuffer Compression type.
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*
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* 0 = none
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* 1 = ROP/3D, layout 1, exact compression format implied by Page
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* Kind field
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* 2 = ROP/3D, layout 2, exact compression format implied by Page
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* Kind field
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* 3 = CDE horizontal
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* 4 = CDE vertical
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* 5 = Reserved for future use
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* 6 = Reserved for future use
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* 7 = Reserved for future use
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*
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* 55:25 - Reserved for future use. Must be zero.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
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fourcc_mod_code(NVIDIA, (0x10 | \
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((h) & 0xf) | \
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(((k) & 0xff) << 12) | \
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(((g) & 0x3) << 20) | \
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(((s) & 0x1) << 22) | \
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(((c) & 0x7) << 23)))
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/* To grandfather in prior block linear format modifiers to the above layout,
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* the page kind "0", which corresponds to "pitch/linear" and hence is unusable
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* with block-linear layouts, is remapped within drivers to the value 0xfe,
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static inline __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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return modifier;
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else
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return modifier | (0xfe << 12);
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}
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/*
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* 16Bx2 Block Linear layout, used by Tegra K1 and later
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*
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* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
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* vertically by a power of 2 (1 to 32 GOBs) to form a block.
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*
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* Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
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*
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* Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
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* Valid values are:
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*
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* 0 == ONE_GOB
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* 1 == TWO_GOBS
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* 2 == FOUR_GOBS
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* 3 == EIGHT_GOBS
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* 4 == SIXTEEN_GOBS
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* 5 == THIRTYTWO_GOBS
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
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DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* DRM_FOURCC_H */
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