281 lines
6.9 KiB
C
281 lines
6.9 KiB
C
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/*
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* linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
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*
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* Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
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*
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* $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#ifndef TGAFB_H
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#define TGAFB_H
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/*
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* TGA hardware description (minimal)
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*/
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#define TGA_TYPE_8PLANE 0
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#define TGA_TYPE_24PLANE 1
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#define TGA_TYPE_24PLUSZ 3
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/*
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* Offsets within Memory Space
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*/
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#define TGA_ROM_OFFSET 0x0000000
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#define TGA_REGS_OFFSET 0x0100000
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#define TGA_8PLANE_FB_OFFSET 0x0200000
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#define TGA_24PLANE_FB_OFFSET 0x0804000
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#define TGA_24PLUSZ_FB_OFFSET 0x1004000
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#define TGA_FOREGROUND_REG 0x0020
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#define TGA_BACKGROUND_REG 0x0024
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#define TGA_PLANEMASK_REG 0x0028
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#define TGA_PIXELMASK_ONESHOT_REG 0x002c
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#define TGA_MODE_REG 0x0030
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#define TGA_RASTEROP_REG 0x0034
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#define TGA_PIXELSHIFT_REG 0x0038
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#define TGA_DEEP_REG 0x0050
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#define TGA_START_REG 0x0054
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#define TGA_PIXELMASK_REG 0x005c
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#define TGA_CURSOR_BASE_REG 0x0060
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#define TGA_HORIZ_REG 0x0064
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#define TGA_VERT_REG 0x0068
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#define TGA_BASE_ADDR_REG 0x006c
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#define TGA_VALID_REG 0x0070
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#define TGA_CURSOR_XY_REG 0x0074
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#define TGA_INTR_STAT_REG 0x007c
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#define TGA_DATA_REG 0x0080
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#define TGA_RAMDAC_SETUP_REG 0x00c0
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#define TGA_BLOCK_COLOR0_REG 0x0140
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#define TGA_BLOCK_COLOR1_REG 0x0144
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#define TGA_BLOCK_COLOR2_REG 0x0148
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#define TGA_BLOCK_COLOR3_REG 0x014c
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#define TGA_BLOCK_COLOR4_REG 0x0150
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#define TGA_BLOCK_COLOR5_REG 0x0154
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#define TGA_BLOCK_COLOR6_REG 0x0158
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#define TGA_BLOCK_COLOR7_REG 0x015c
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#define TGA_COPY64_SRC 0x0160
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#define TGA_COPY64_DST 0x0164
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#define TGA_CLOCK_REG 0x01e8
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#define TGA_RAMDAC_REG 0x01f0
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#define TGA_CMD_STAT_REG 0x01f8
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/*
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* Useful defines for managing the registers
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*/
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#define TGA_HORIZ_ODD 0x80000000
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#define TGA_HORIZ_POLARITY 0x40000000
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#define TGA_HORIZ_ACT_MSB 0x30000000
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#define TGA_HORIZ_BP 0x0fe00000
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#define TGA_HORIZ_SYNC 0x001fc000
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#define TGA_HORIZ_FP 0x00007c00
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#define TGA_HORIZ_ACT_LSB 0x000001ff
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#define TGA_VERT_SE 0x80000000
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#define TGA_VERT_POLARITY 0x40000000
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#define TGA_VERT_RESERVED 0x30000000
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#define TGA_VERT_BP 0x0fc00000
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#define TGA_VERT_SYNC 0x003f0000
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#define TGA_VERT_FP 0x0000f800
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#define TGA_VERT_ACTIVE 0x000007ff
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#define TGA_VALID_VIDEO 0x01
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#define TGA_VALID_BLANK 0x02
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#define TGA_VALID_CURSOR 0x04
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#define TGA_MODE_SBM_8BPP 0x000
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#define TGA_MODE_SBM_24BPP 0x300
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#define TGA_MODE_SIMPLE 0x00
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#define TGA_MODE_SIMPLEZ 0x10
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#define TGA_MODE_OPAQUE_STIPPLE 0x01
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#define TGA_MODE_OPAQUE_FILL 0x21
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#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
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#define TGA_MODE_TRANSPARENT_FILL 0x23
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#define TGA_MODE_BLOCK_STIPPLE 0x0d
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#define TGA_MODE_BLOCK_FILL 0x2d
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#define TGA_MODE_COPY 0x07
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#define TGA_MODE_DMA_READ_COPY_ND 0x17
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#define TGA_MODE_DMA_READ_COPY_D 0x37
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#define TGA_MODE_DMA_WRITE_COPY 0x1f
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/*
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* Useful defines for managing the ICS1562 PLL clock
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*/
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#define TGA_PLL_BASE_FREQ 14318 /* .18 */
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#define TGA_PLL_MAX_FREQ 230000
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/*
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* Useful defines for managing the BT485 on the 8-plane TGA
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*/
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#define BT485_READ_BIT 0x01
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#define BT485_WRITE_BIT 0x00
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#define BT485_ADDR_PAL_WRITE 0x00
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#define BT485_DATA_PAL 0x02
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#define BT485_PIXEL_MASK 0x04
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#define BT485_ADDR_PAL_READ 0x06
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#define BT485_ADDR_CUR_WRITE 0x08
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#define BT485_DATA_CUR 0x0a
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#define BT485_CMD_0 0x0c
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#define BT485_ADDR_CUR_READ 0x0e
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#define BT485_CMD_1 0x10
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#define BT485_CMD_2 0x12
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#define BT485_STATUS 0x14
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#define BT485_CMD_3 0x14
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#define BT485_CUR_RAM 0x16
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#define BT485_CUR_LOW_X 0x18
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#define BT485_CUR_HIGH_X 0x1a
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#define BT485_CUR_LOW_Y 0x1c
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#define BT485_CUR_HIGH_Y 0x1e
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/*
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* Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s
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*/
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#define BT463_ADDR_LO 0x0
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#define BT463_ADDR_HI 0x1
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#define BT463_REG_ACC 0x2
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#define BT463_PALETTE 0x3
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#define BT463_CUR_CLR_0 0x0100
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#define BT463_CUR_CLR_1 0x0101
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#define BT463_CMD_REG_0 0x0201
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#define BT463_CMD_REG_1 0x0202
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#define BT463_CMD_REG_2 0x0203
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#define BT463_READ_MASK_0 0x0205
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#define BT463_READ_MASK_1 0x0206
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#define BT463_READ_MASK_2 0x0207
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#define BT463_READ_MASK_3 0x0208
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#define BT463_BLINK_MASK_0 0x0209
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#define BT463_BLINK_MASK_1 0x020a
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#define BT463_BLINK_MASK_2 0x020b
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#define BT463_BLINK_MASK_3 0x020c
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#define BT463_WINDOW_TYPE_BASE 0x0300
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/*
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* Useful defines for managing the BT459 on the 8-plane SFB+s
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*/
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#define BT459_ADDR_LO 0x0
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#define BT459_ADDR_HI 0x1
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#define BT459_REG_ACC 0x2
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#define BT459_PALETTE 0x3
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#define BT459_CUR_CLR_1 0x0181
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#define BT459_CUR_CLR_2 0x0182
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#define BT459_CUR_CLR_3 0x0183
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#define BT459_CMD_REG_0 0x0201
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#define BT459_CMD_REG_1 0x0202
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#define BT459_CMD_REG_2 0x0203
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#define BT459_READ_MASK 0x0204
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#define BT459_BLINK_MASK 0x0206
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#define BT459_CUR_CMD_REG 0x0300
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/*
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* The framebuffer driver private data.
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*/
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struct tga_par {
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/* PCI/TC device. */
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struct device *dev;
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/* Device dependent information. */
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void __iomem *tga_mem_base;
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void __iomem *tga_fb_base;
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void __iomem *tga_regs_base;
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u8 tga_type; /* TGA_TYPE_XXX */
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u8 tga_chip_rev; /* dc21030 revision */
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/* Remember blank mode. */
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u8 vesa_blanked;
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/* Define the video mode. */
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u32 xres, yres; /* resolution in pixels */
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u32 htimings; /* horizontal timing register */
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u32 vtimings; /* vertical timing register */
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u32 pll_freq; /* pixclock in mhz */
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u32 bits_per_pixel; /* bits per pixel */
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u32 sync_on_green; /* set if sync is on green */
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u32 palette[16];
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};
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/*
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* Macros for reading/writing TGA and RAMDAC registers
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*/
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static inline void
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TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
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{
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writel(v, par->tga_regs_base +r);
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}
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static inline u32
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TGA_READ_REG(struct tga_par *par, u32 r)
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{
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return readl(par->tga_regs_base +r);
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}
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static inline void
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BT485_WRITE(struct tga_par *par, u8 v, u8 r)
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{
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TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
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}
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static inline void
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BT463_LOAD_ADDR(struct tga_par *par, u16 a)
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{
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TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
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}
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static inline void
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BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
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{
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BT463_LOAD_ADDR(par, a);
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TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
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}
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static inline void
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BT459_LOAD_ADDR(struct tga_par *par, u16 a)
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{
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TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
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}
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static inline void
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BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
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{
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BT459_LOAD_ADDR(par, a);
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TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
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}
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#endif /* TGAFB_H */
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