233 lines
7.1 KiB
C
233 lines
7.1 KiB
C
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/*
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* Common functionality for the alsa driver code base for HD Audio.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SOUND_HDA_CONTROLLER_H
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#define __SOUND_HDA_CONTROLLER_H
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#include <linux/timecounter.h>
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#include <linux/interrupt.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include "hda_codec.h"
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#include <sound/hda_register.h>
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#define AZX_MAX_CODECS HDA_MAX_CODECS
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#define AZX_DEFAULT_CODECS 4
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/* driver quirks (capabilities) */
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/* bits 0-7 are used for indicating driver type */
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#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
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#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
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#define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */
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#define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */
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/* 13 unused */
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/* 14 unused */
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#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
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#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
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/* 17 unused */
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#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
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#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
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#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
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#define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */
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/* 22 unused */
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#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
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/* 24 unused */
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#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
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#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
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#ifdef CONFIG_SND_HDA_I915
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#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
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#else
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#define AZX_DCAPS_I915_POWERWELL 0 /* NOP */
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#endif
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#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
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#define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
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#define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
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enum {
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AZX_SNOOP_TYPE_NONE,
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AZX_SNOOP_TYPE_SCH,
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AZX_SNOOP_TYPE_ATI,
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AZX_SNOOP_TYPE_NVIDIA,
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};
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struct azx_dev {
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struct hdac_stream core;
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unsigned int irq_pending:1;
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/*
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* For VIA:
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* A flag to ensure DMA position is 0
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* when link position is not greater than FIFO size
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*/
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unsigned int insufficient:1;
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unsigned int wc_marked:1;
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};
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#define azx_stream(dev) (&(dev)->core)
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#define stream_to_azx_dev(s) container_of(s, struct azx_dev, core)
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struct azx;
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/* Functions to read/write to hda registers. */
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struct hda_controller_ops {
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/* Disable msi if supported, PCI only */
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int (*disable_msi_reset_irq)(struct azx *);
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int (*substream_alloc_pages)(struct azx *chip,
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struct snd_pcm_substream *substream,
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size_t size);
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int (*substream_free_pages)(struct azx *chip,
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struct snd_pcm_substream *substream);
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void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
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struct vm_area_struct *area);
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/* Check if current position is acceptable */
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int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
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/* enable/disable the link power */
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int (*link_power)(struct azx *chip, bool enable);
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};
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struct azx_pcm {
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struct azx *chip;
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struct snd_pcm *pcm;
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struct hda_codec *codec;
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struct hda_pcm *info;
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struct list_head list;
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};
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typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
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typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
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struct azx {
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struct hda_bus bus;
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struct snd_card *card;
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struct pci_dev *pci;
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int dev_index;
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/* chip type specific */
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int driver_type;
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unsigned int driver_caps;
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int playback_streams;
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int playback_index_offset;
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int capture_streams;
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int capture_index_offset;
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int num_streams;
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const int *jackpoll_ms; /* per-card jack poll interval */
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/* Register interaction. */
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const struct hda_controller_ops *ops;
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/* position adjustment callbacks */
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azx_get_pos_callback_t get_position[2];
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azx_get_delay_callback_t get_delay[2];
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/* locks */
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struct mutex open_mutex; /* Prevents concurrent open/close operations */
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/* PCM */
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struct list_head pcm_list; /* azx_pcm list */
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/* HD codec */
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int codec_probe_mask; /* copied from probe_mask option */
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unsigned int beep_mode;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
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const struct firmware *fw;
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#endif
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/* flags */
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int bdl_pos_adj;
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int poll_count;
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unsigned int running:1;
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unsigned int single_cmd:1;
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unsigned int polling_mode:1;
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unsigned int msi:1;
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unsigned int probing:1; /* codec probing phase */
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unsigned int snoop:1;
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unsigned int uc_buffer:1; /* non-cached pages for stream buffers */
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unsigned int align_buffer_size:1;
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unsigned int region_requested:1;
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unsigned int disabled:1; /* disabled by vga_switcheroo */
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/* GTS present */
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unsigned int gts_present:1;
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#ifdef CONFIG_SND_HDA_DSP_LOADER
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struct azx_dev saved_azx_dev;
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#endif
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};
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#define azx_bus(chip) (&(chip)->bus.core)
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#define bus_to_azx(_bus) container_of(_bus, struct azx, bus.core)
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static inline bool azx_snoop(struct azx *chip)
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{
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return !IS_ENABLED(CONFIG_X86) || chip->snoop;
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}
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/*
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* macros for easy use
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*/
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#define azx_writel(chip, reg, value) \
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snd_hdac_chip_writel(azx_bus(chip), reg, value)
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#define azx_readl(chip, reg) \
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snd_hdac_chip_readl(azx_bus(chip), reg)
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#define azx_writew(chip, reg, value) \
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snd_hdac_chip_writew(azx_bus(chip), reg, value)
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#define azx_readw(chip, reg) \
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snd_hdac_chip_readw(azx_bus(chip), reg)
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#define azx_writeb(chip, reg, value) \
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snd_hdac_chip_writeb(azx_bus(chip), reg, value)
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#define azx_readb(chip, reg) \
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snd_hdac_chip_readb(azx_bus(chip), reg)
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#define azx_has_pm_runtime(chip) \
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((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME)
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/* PCM setup */
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static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
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{
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return substream->runtime->private_data;
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}
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unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
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unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
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unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
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/* Stream control. */
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void azx_stop_all_streams(struct azx *chip);
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/* Allocation functions. */
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#define azx_alloc_stream_pages(chip) \
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snd_hdac_bus_alloc_stream_pages(azx_bus(chip))
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#define azx_free_stream_pages(chip) \
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snd_hdac_bus_free_stream_pages(azx_bus(chip))
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/* Low level azx interface */
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void azx_init_chip(struct azx *chip, bool full_reset);
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void azx_stop_chip(struct azx *chip);
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#define azx_enter_link_reset(chip) \
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snd_hdac_bus_enter_link_reset(azx_bus(chip))
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irqreturn_t azx_interrupt(int irq, void *dev_id);
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/* Codec interface */
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int azx_bus_init(struct azx *chip, const char *model,
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const struct hdac_io_ops *io_ops);
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int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
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int azx_codec_configure(struct azx *chip);
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int azx_init_streams(struct azx *chip);
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void azx_free_streams(struct azx *chip);
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#endif /* __SOUND_HDA_CONTROLLER_H */
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