324 lines
7.3 KiB
C
324 lines
7.3 KiB
C
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/*
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* Au1000/Au1500/Au1100 I2S controller driver for ASoC
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*
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* (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
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*
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* Note: clock supplied to the I2S controller must be 256x samplerate.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/suspend.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/mach-au1x00/au1000.h>
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#include "psc.h"
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#define I2S_RXTX 0x00
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#define I2S_CFG 0x04
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#define I2S_ENABLE 0x08
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#define CFG_XU (1 << 25) /* tx underflow */
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#define CFG_XO (1 << 24)
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#define CFG_RU (1 << 23)
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#define CFG_RO (1 << 22)
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#define CFG_TR (1 << 21)
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#define CFG_TE (1 << 20)
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#define CFG_TF (1 << 19)
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#define CFG_RR (1 << 18)
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#define CFG_RF (1 << 17)
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#define CFG_ICK (1 << 12) /* clock invert */
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#define CFG_PD (1 << 11) /* set to make I2SDIO INPUT */
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#define CFG_LB (1 << 10) /* loopback */
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#define CFG_IC (1 << 9) /* word select invert */
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#define CFG_FM_I2S (0 << 7) /* I2S format */
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#define CFG_FM_LJ (1 << 7) /* left-justified */
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#define CFG_FM_RJ (2 << 7) /* right-justified */
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#define CFG_FM_MASK (3 << 7)
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#define CFG_TN (1 << 6) /* tx fifo en */
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#define CFG_RN (1 << 5) /* rx fifo en */
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#define CFG_SZ_8 (0x08)
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#define CFG_SZ_16 (0x10)
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#define CFG_SZ_18 (0x12)
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#define CFG_SZ_20 (0x14)
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#define CFG_SZ_24 (0x18)
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#define CFG_SZ_MASK (0x1f)
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#define EN_D (1 << 1) /* DISable */
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#define EN_CE (1 << 0) /* clock enable */
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/* only limited by clock generator and board design */
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#define AU1XI2SC_RATES \
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SNDRV_PCM_RATE_CONTINUOUS
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#define AU1XI2SC_FMTS \
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(SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
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SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
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SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
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SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
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SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_U18_3BE | \
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SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
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SNDRV_PCM_FMTBIT_S20_3BE | SNDRV_PCM_FMTBIT_U20_3BE | \
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SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
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SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
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0)
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static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
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{
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return __raw_readl(ctx->mmio + reg);
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}
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static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
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{
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__raw_writel(v, ctx->mmio + reg);
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wmb();
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}
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static int au1xi2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned long c;
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int ret;
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ret = -EINVAL;
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c = ctx->cfg;
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c &= ~CFG_FM_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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c |= CFG_FM_I2S;
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break;
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case SND_SOC_DAIFMT_MSB:
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c |= CFG_FM_RJ;
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break;
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case SND_SOC_DAIFMT_LSB:
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c |= CFG_FM_LJ;
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break;
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default:
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goto out;
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}
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c &= ~(CFG_IC | CFG_ICK); /* IB-IF */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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c |= CFG_IC | CFG_ICK;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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c |= CFG_IC;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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c |= CFG_ICK;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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break;
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default:
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goto out;
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}
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/* I2S controller only supports master */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS: /* CODEC slave */
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break;
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default:
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goto out;
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}
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ret = 0;
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ctx->cfg = c;
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out:
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return ret;
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}
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static int au1xi2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
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int stype = SUBSTREAM_TYPE(substream);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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/* power up */
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WR(ctx, I2S_ENABLE, EN_D | EN_CE);
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WR(ctx, I2S_ENABLE, EN_CE);
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ctx->cfg |= (stype == PCM_TX) ? CFG_TN : CFG_RN;
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WR(ctx, I2S_CFG, ctx->cfg);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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ctx->cfg &= ~((stype == PCM_TX) ? CFG_TN : CFG_RN);
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WR(ctx, I2S_CFG, ctx->cfg);
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WR(ctx, I2S_ENABLE, EN_D); /* power off */
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static unsigned long msbits_to_reg(int msbits)
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{
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switch (msbits) {
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case 8:
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return CFG_SZ_8;
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case 16:
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return CFG_SZ_16;
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case 18:
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return CFG_SZ_18;
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case 20:
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return CFG_SZ_20;
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case 24:
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return CFG_SZ_24;
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}
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return 0;
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}
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static int au1xi2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
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unsigned long v;
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v = msbits_to_reg(params->msbits);
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if (!v)
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return -EINVAL;
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ctx->cfg &= ~CFG_SZ_MASK;
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ctx->cfg |= v;
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return 0;
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}
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static int au1xi2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
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return 0;
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}
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static const struct snd_soc_dai_ops au1xi2s_dai_ops = {
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.startup = au1xi2s_startup,
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.trigger = au1xi2s_trigger,
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.hw_params = au1xi2s_hw_params,
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.set_fmt = au1xi2s_set_fmt,
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};
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static struct snd_soc_dai_driver au1xi2s_dai_driver = {
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.symmetric_rates = 1,
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.playback = {
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.rates = AU1XI2SC_RATES,
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.formats = AU1XI2SC_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.capture = {
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.rates = AU1XI2SC_RATES,
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.formats = AU1XI2SC_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.ops = &au1xi2s_dai_ops,
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};
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static const struct snd_soc_component_driver au1xi2s_component = {
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.name = "au1xi2s",
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};
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static int au1xi2s_drvprobe(struct platform_device *pdev)
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{
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struct resource *iores, *dmares;
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struct au1xpsc_audio_data *ctx;
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ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, iores->start,
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resource_size(iores),
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pdev->name))
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return -EBUSY;
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ctx->mmio = devm_ioremap_nocache(&pdev->dev, iores->start,
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resource_size(iores));
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if (!ctx->mmio)
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return -EBUSY;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!dmares)
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return -EBUSY;
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ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (!dmares)
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return -EBUSY;
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ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
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platform_set_drvdata(pdev, ctx);
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return snd_soc_register_component(&pdev->dev, &au1xi2s_component,
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&au1xi2s_dai_driver, 1);
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}
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static int au1xi2s_drvremove(struct platform_device *pdev)
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{
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struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
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snd_soc_unregister_component(&pdev->dev);
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WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */
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return 0;
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}
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#ifdef CONFIG_PM
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static int au1xi2s_drvsuspend(struct device *dev)
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{
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struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
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WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */
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return 0;
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}
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static int au1xi2s_drvresume(struct device *dev)
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{
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return 0;
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}
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static const struct dev_pm_ops au1xi2sc_pmops = {
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.suspend = au1xi2s_drvsuspend,
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.resume = au1xi2s_drvresume,
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};
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#define AU1XI2SC_PMOPS (&au1xi2sc_pmops)
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#else
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#define AU1XI2SC_PMOPS NULL
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#endif
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static struct platform_driver au1xi2s_driver = {
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.driver = {
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.name = "alchemy-i2sc",
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.pm = AU1XI2SC_PMOPS,
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},
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.probe = au1xi2s_drvprobe,
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.remove = au1xi2s_drvremove,
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};
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module_platform_driver(au1xi2s_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Au1000/1500/1100 I2S ASoC driver");
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MODULE_AUTHOR("Manuel Lauss");
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