463 lines
11 KiB
C
463 lines
11 KiB
C
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/*
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* skl-sst-dsp.c - SKL SST library generic function
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*
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* Copyright (C) 2014-15, Intel Corporation.
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* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
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* Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <sound/pcm.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-ipc.h"
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#include "../common/sst-dsp-priv.h"
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#include "skl-sst-ipc.h"
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/* various timeout values */
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#define SKL_DSP_PU_TO 50
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#define SKL_DSP_PD_TO 50
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#define SKL_DSP_RESET_TO 50
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void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state)
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{
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mutex_lock(&ctx->mutex);
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ctx->sst_state = state;
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mutex_unlock(&ctx->mutex);
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}
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/*
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* Initialize core power state and usage count. To be called after
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* successful first boot. Hence core 0 will be running and other cores
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* will be reset
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*/
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void skl_dsp_init_core_state(struct sst_dsp *ctx)
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{
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struct skl_sst *skl = ctx->thread_context;
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int i;
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skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
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skl->cores.usage_count[SKL_DSP_CORE0_ID] = 1;
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for (i = SKL_DSP_CORE0_ID + 1; i < SKL_DSP_CORES_MAX; i++) {
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skl->cores.state[i] = SKL_DSP_RESET;
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skl->cores.usage_count[i] = 0;
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}
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}
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/* Get the mask for all enabled cores */
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unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx)
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{
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struct skl_sst *skl = ctx->thread_context;
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unsigned int core_mask, en_cores_mask;
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u32 val;
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core_mask = SKL_DSP_CORES_MASK(skl->cores.count);
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val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS);
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/* Cores having CPA bit set */
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en_cores_mask = (val & SKL_ADSPCS_CPA_MASK(core_mask)) >>
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SKL_ADSPCS_CPA_SHIFT;
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/* And cores having CRST bit cleared */
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en_cores_mask &= (~val & SKL_ADSPCS_CRST_MASK(core_mask)) >>
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SKL_ADSPCS_CRST_SHIFT;
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/* And cores having CSTALL bit cleared */
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en_cores_mask &= (~val & SKL_ADSPCS_CSTALL_MASK(core_mask)) >>
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SKL_ADSPCS_CSTALL_SHIFT;
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en_cores_mask &= core_mask;
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dev_dbg(ctx->dev, "DSP enabled cores mask = %x\n", en_cores_mask);
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return en_cores_mask;
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}
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static int
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skl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK(core_mask),
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SKL_ADSPCS_CRST_MASK(core_mask));
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/* poll with timeout to check if operation successful */
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ret = sst_dsp_register_poll(ctx,
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SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CRST_MASK(core_mask),
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SKL_ADSPCS_CRST_MASK(core_mask),
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SKL_DSP_RESET_TO,
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"Set reset");
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if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
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SKL_ADSPCS_CRST_MASK(core_mask)) !=
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SKL_ADSPCS_CRST_MASK(core_mask)) {
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dev_err(ctx->dev, "Set reset state failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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int skl_dsp_core_unset_reset_state(
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struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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dev_dbg(ctx->dev, "In %s\n", __func__);
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CRST_MASK(core_mask), 0);
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/* poll with timeout to check if operation successful */
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ret = sst_dsp_register_poll(ctx,
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SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CRST_MASK(core_mask),
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0,
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SKL_DSP_RESET_TO,
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"Unset reset");
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if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
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SKL_ADSPCS_CRST_MASK(core_mask)) != 0) {
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dev_err(ctx->dev, "Unset reset state failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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static bool
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is_skl_dsp_core_enable(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int val;
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bool is_enable;
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val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS);
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is_enable = ((val & SKL_ADSPCS_CPA_MASK(core_mask)) &&
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(val & SKL_ADSPCS_SPA_MASK(core_mask)) &&
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!(val & SKL_ADSPCS_CRST_MASK(core_mask)) &&
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!(val & SKL_ADSPCS_CSTALL_MASK(core_mask)));
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dev_dbg(ctx->dev, "DSP core(s) enabled? %d : core_mask %x\n",
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is_enable, core_mask);
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return is_enable;
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}
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static int skl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* stall core */
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CSTALL_MASK(core_mask),
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SKL_ADSPCS_CSTALL_MASK(core_mask));
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/* set reset state */
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return skl_dsp_core_set_reset_state(ctx, core_mask);
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}
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int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* unset reset state */
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ret = skl_dsp_core_unset_reset_state(ctx, core_mask);
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if (ret < 0)
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return ret;
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/* run core */
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dev_dbg(ctx->dev, "unstall/run core: core_mask = %x\n", core_mask);
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CSTALL_MASK(core_mask), 0);
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if (!is_skl_dsp_core_enable(ctx, core_mask)) {
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skl_dsp_reset_core(ctx, core_mask);
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dev_err(ctx->dev, "DSP start core failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_SPA_MASK(core_mask),
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SKL_ADSPCS_SPA_MASK(core_mask));
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/* poll with timeout to check if operation successful */
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ret = sst_dsp_register_poll(ctx,
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SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CPA_MASK(core_mask),
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SKL_ADSPCS_CPA_MASK(core_mask),
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SKL_DSP_PU_TO,
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"Power up");
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if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) &
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SKL_ADSPCS_CPA_MASK(core_mask)) !=
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SKL_ADSPCS_CPA_MASK(core_mask)) {
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dev_err(ctx->dev, "DSP core power up failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_SPA_MASK(core_mask), 0);
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/* poll with timeout to check if operation successful */
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return sst_dsp_register_poll(ctx,
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SKL_ADSP_REG_ADSPCS,
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SKL_ADSPCS_CPA_MASK(core_mask),
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0,
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SKL_DSP_PD_TO,
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"Power down");
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}
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int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* power up */
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ret = skl_dsp_core_power_up(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core power up failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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return skl_dsp_start_core(ctx, core_mask);
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}
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int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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ret = skl_dsp_reset_core(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core reset failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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/* power down core*/
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ret = skl_dsp_core_power_down(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core power down fail mask %x: %d\n",
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core_mask, ret);
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return ret;
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}
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if (is_skl_dsp_core_enable(ctx, core_mask)) {
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dev_err(ctx->dev, "dsp core disable fail mask %x: %d\n",
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core_mask, ret);
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ret = -EIO;
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}
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return ret;
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}
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int skl_dsp_boot(struct sst_dsp *ctx)
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{
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int ret;
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if (is_skl_dsp_core_enable(ctx, SKL_DSP_CORE0_MASK)) {
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ret = skl_dsp_reset_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core0 reset fail: %d\n", ret);
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return ret;
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}
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ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core0 start fail: %d\n", ret);
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return ret;
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}
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} else {
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ret = skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core0 disable fail: %d\n", ret);
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return ret;
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}
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ret = skl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
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}
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return ret;
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}
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irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id)
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{
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struct sst_dsp *ctx = dev_id;
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u32 val;
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irqreturn_t result = IRQ_NONE;
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spin_lock(&ctx->spinlock);
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val = sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPIS);
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ctx->intr_status = val;
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if (val == 0xffffffff) {
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spin_unlock(&ctx->spinlock);
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return IRQ_NONE;
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}
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if (val & SKL_ADSPIS_IPC) {
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skl_ipc_int_disable(ctx);
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result = IRQ_WAKE_THREAD;
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}
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if (val & SKL_ADSPIS_CL_DMA) {
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skl_cldma_int_disable(ctx);
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result = IRQ_WAKE_THREAD;
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}
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spin_unlock(&ctx->spinlock);
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return result;
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}
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/*
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* skl_dsp_get_core/skl_dsp_put_core will be called inside DAPM context
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* within the dapm mutex. Hence no separate lock is used.
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*/
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int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id)
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{
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struct skl_sst *skl = ctx->thread_context;
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int ret = 0;
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if (core_id >= skl->cores.count) {
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dev_err(ctx->dev, "invalid core id: %d\n", core_id);
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return -EINVAL;
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}
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if (skl->cores.state[core_id] == SKL_DSP_RESET) {
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ret = ctx->fw_ops.set_state_D0(ctx, core_id);
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||
|
|
if (ret < 0) {
|
||
|
|
dev_err(ctx->dev, "unable to get core%d\n", core_id);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
skl->cores.usage_count[core_id]++;
|
||
|
|
|
||
|
|
dev_dbg(ctx->dev, "core id %d state %d usage_count %d\n",
|
||
|
|
core_id, skl->cores.state[core_id],
|
||
|
|
skl->cores.usage_count[core_id]);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(skl_dsp_get_core);
|
||
|
|
|
||
|
|
int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id)
|
||
|
|
{
|
||
|
|
struct skl_sst *skl = ctx->thread_context;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (core_id >= skl->cores.count) {
|
||
|
|
dev_err(ctx->dev, "invalid core id: %d\n", core_id);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (--skl->cores.usage_count[core_id] == 0) {
|
||
|
|
ret = ctx->fw_ops.set_state_D3(ctx, core_id);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(ctx->dev, "unable to put core %d: %d\n",
|
||
|
|
core_id, ret);
|
||
|
|
skl->cores.usage_count[core_id]++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_dbg(ctx->dev, "core id %d state %d usage_count %d\n",
|
||
|
|
core_id, skl->cores.state[core_id],
|
||
|
|
skl->cores.usage_count[core_id]);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(skl_dsp_put_core);
|
||
|
|
|
||
|
|
int skl_dsp_wake(struct sst_dsp *ctx)
|
||
|
|
{
|
||
|
|
return skl_dsp_get_core(ctx, SKL_DSP_CORE0_ID);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(skl_dsp_wake);
|
||
|
|
|
||
|
|
int skl_dsp_sleep(struct sst_dsp *ctx)
|
||
|
|
{
|
||
|
|
return skl_dsp_put_core(ctx, SKL_DSP_CORE0_ID);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(skl_dsp_sleep);
|
||
|
|
|
||
|
|
struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
|
||
|
|
struct sst_dsp_device *sst_dev, int irq)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct sst_dsp *sst;
|
||
|
|
|
||
|
|
sst = devm_kzalloc(dev, sizeof(*sst), GFP_KERNEL);
|
||
|
|
if (sst == NULL)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
spin_lock_init(&sst->spinlock);
|
||
|
|
mutex_init(&sst->mutex);
|
||
|
|
sst->dev = dev;
|
||
|
|
sst->sst_dev = sst_dev;
|
||
|
|
sst->irq = irq;
|
||
|
|
sst->ops = sst_dev->ops;
|
||
|
|
sst->thread_context = sst_dev->thread_context;
|
||
|
|
|
||
|
|
/* Initialise SST Audio DSP */
|
||
|
|
if (sst->ops->init) {
|
||
|
|
ret = sst->ops->init(sst, NULL);
|
||
|
|
if (ret < 0)
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Register the ISR */
|
||
|
|
ret = request_threaded_irq(sst->irq, sst->ops->irq_handler,
|
||
|
|
sst_dev->thread, IRQF_SHARED, "AudioDSP", sst);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(sst->dev, "unable to grab threaded IRQ %d, disabling device\n",
|
||
|
|
sst->irq);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return sst;
|
||
|
|
}
|
||
|
|
|
||
|
|
void skl_dsp_free(struct sst_dsp *dsp)
|
||
|
|
{
|
||
|
|
skl_ipc_int_disable(dsp);
|
||
|
|
|
||
|
|
free_irq(dsp->irq, dsp);
|
||
|
|
skl_ipc_op_int_disable(dsp);
|
||
|
|
skl_dsp_disable_core(dsp, SKL_DSP_CORE0_MASK);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(skl_dsp_free);
|
||
|
|
|
||
|
|
bool is_skl_dsp_running(struct sst_dsp *ctx)
|
||
|
|
{
|
||
|
|
return (ctx->sst_state == SKL_DSP_RUNNING);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(is_skl_dsp_running);
|