187 lines
5.8 KiB
C
187 lines
5.8 KiB
C
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/*
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* mt2701-reg.h -- Mediatek 2701 audio driver reg definition
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Garlic Tseng <garlic.tseng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MT2701_REG_H_
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#define _MT2701_REG_H_
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_runtime.h>
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#include <sound/soc.h>
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#include "mt2701-afe-common.h"
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/*****************************************************************************
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* R E G I S T E R D E F I N I T I O N
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*****************************************************************************/
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#define AUDIO_TOP_CON0 0x0000
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#define AUDIO_TOP_CON4 0x0010
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#define AUDIO_TOP_CON5 0x0014
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#define AFE_DAIBT_CON0 0x001c
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#define AFE_MRGIF_CON 0x003c
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#define ASMI_TIMING_CON1 0x0100
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#define ASMO_TIMING_CON1 0x0104
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#define PWR1_ASM_CON1 0x0108
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#define ASYS_TOP_CON 0x0600
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#define ASYS_I2SIN1_CON 0x0604
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#define ASYS_I2SIN2_CON 0x0608
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#define ASYS_I2SIN3_CON 0x060c
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#define ASYS_I2SIN4_CON 0x0610
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#define ASYS_I2SIN5_CON 0x0614
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#define ASYS_I2SO1_CON 0x061C
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#define ASYS_I2SO2_CON 0x0620
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#define ASYS_I2SO3_CON 0x0624
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#define ASYS_I2SO4_CON 0x0628
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#define ASYS_I2SO5_CON 0x062c
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#define PWR2_TOP_CON 0x0634
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#define AFE_CONN0 0x06c0
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#define AFE_CONN1 0x06c4
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#define AFE_CONN2 0x06c8
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#define AFE_CONN3 0x06cc
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#define AFE_CONN14 0x06f8
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#define AFE_CONN15 0x06fc
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#define AFE_CONN16 0x0700
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#define AFE_CONN17 0x0704
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#define AFE_CONN18 0x0708
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#define AFE_CONN19 0x070c
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#define AFE_CONN20 0x0710
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#define AFE_CONN21 0x0714
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#define AFE_CONN22 0x0718
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#define AFE_CONN23 0x071c
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#define AFE_CONN24 0x0720
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#define AFE_CONN41 0x0764
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#define ASYS_IRQ1_CON 0x0780
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#define ASYS_IRQ2_CON 0x0784
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#define ASYS_IRQ3_CON 0x0788
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#define ASYS_IRQ_CLR 0x07c0
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#define ASYS_IRQ_STATUS 0x07c4
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#define PWR2_ASM_CON1 0x1070
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#define AFE_DAC_CON0 0x1200
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#define AFE_DAC_CON1 0x1204
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#define AFE_DAC_CON2 0x1208
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#define AFE_DAC_CON3 0x120c
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#define AFE_DAC_CON4 0x1210
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#define AFE_MEMIF_HD_CON1 0x121c
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#define AFE_MEMIF_PBUF_SIZE 0x1238
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#define AFE_MEMIF_HD_CON0 0x123c
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#define AFE_DL1_BASE 0x1240
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#define AFE_DL1_CUR 0x1244
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#define AFE_DL2_BASE 0x1250
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#define AFE_DL2_CUR 0x1254
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#define AFE_DL3_BASE 0x1260
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#define AFE_DL3_CUR 0x1264
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#define AFE_DL4_BASE 0x1270
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#define AFE_DL4_CUR 0x1274
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#define AFE_DL5_BASE 0x1280
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#define AFE_DL5_CUR 0x1284
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#define AFE_DLMCH_BASE 0x12a0
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#define AFE_DLMCH_CUR 0x12a4
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#define AFE_ARB1_BASE 0x12b0
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#define AFE_ARB1_CUR 0x12b4
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#define AFE_VUL_BASE 0x1300
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#define AFE_VUL_CUR 0x130c
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#define AFE_UL2_BASE 0x1310
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#define AFE_UL2_END 0x1318
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#define AFE_UL2_CUR 0x131c
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#define AFE_UL3_BASE 0x1320
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#define AFE_UL3_END 0x1328
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#define AFE_UL3_CUR 0x132c
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#define AFE_UL4_BASE 0x1330
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#define AFE_UL4_END 0x1338
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#define AFE_UL4_CUR 0x133c
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#define AFE_UL5_BASE 0x1340
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#define AFE_UL5_END 0x1348
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#define AFE_UL5_CUR 0x134c
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#define AFE_DAI_BASE 0x1370
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#define AFE_DAI_CUR 0x137c
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/* AUDIO_TOP_CON0 (0x0000) */
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#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
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#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
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#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
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/* AUDIO_TOP_CON4 (0x0010) */
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#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
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#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
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#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
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#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
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#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
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/* AFE_DAIBT_CON0 (0x001c) */
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#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
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#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
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#define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)
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#define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)
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#define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)
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/* PWR1_ASM_CON1 (0x0108) */
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#define PWR1_ASM_CON1_INIT_VAL (0x492)
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/* AFE_MRGIF_CON (0x003c) */
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#define AFE_MRGIF_CON_MRG_EN (0x1 << 0)
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#define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)
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#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
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#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
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/* ASYS_I2SO1_CON (0x061c) */
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#define ASYS_I2SO1_CON_FS (0x1f << 8)
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#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
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#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
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#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
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#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
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/* 0:EIAJ 1:I2S */
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#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
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#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
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#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
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/* PWR2_TOP_CON (0x0634) */
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#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
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/* ASYS_IRQ_CLR (0x07c0) */
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#define ASYS_IRQ_CLR_ALL (0xffffffff)
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/* PWR2_ASM_CON1 (0x1070) */
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#define PWR2_ASM_CON1_INIT_VAL (0x492492)
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/* AFE_DAC_CON0 (0x1200) */
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#define AFE_DAC_CON0_AFE_ON (0x1 << 0)
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/* AFE_MEMIF_PBUF_SIZE (0x1238) */
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#define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)
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#define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29)
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#define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29)
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#define DLMCH_BIT_WIDTH_MASK (0x1 << 28)
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#define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24)
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#define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24)
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#define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12)
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#define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12)
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/* I2S in/out register bit control */
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#define ASYS_I2S_CON_FS (0x1f << 8)
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#define ASYS_I2S_CON_FS_SET(x) ((x) << 8)
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#define ASYS_I2S_CON_RESET (0x1 << 30)
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#define ASYS_I2S_CON_I2S_EN (0x1 << 0)
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#define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17)
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/* 0:EIAJ 1:I2S */
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#define ASYS_I2S_CON_I2S_MODE (0x1 << 3)
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#define ASYS_I2S_CON_WIDE_MODE (0x1 << 1)
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#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
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#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
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#define AFE_END_ADDR 0x15e0
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#endif
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