497 lines
9.9 KiB
C
497 lines
9.9 KiB
C
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/*
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* Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#define unlikely(cond) (cond)
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#include <asm/insn.h>
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#include "lib/inat.c"
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#include "lib/insn.c"
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#include "../../elf.h"
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#include "../../arch.h"
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#include "../../warn.h"
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static unsigned char op_to_cfi_reg[][2] = {
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{CFI_AX, CFI_R8},
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{CFI_CX, CFI_R9},
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{CFI_DX, CFI_R10},
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{CFI_BX, CFI_R11},
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{CFI_SP, CFI_R12},
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{CFI_BP, CFI_R13},
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{CFI_SI, CFI_R14},
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{CFI_DI, CFI_R15},
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};
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static int is_x86_64(struct elf *elf)
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{
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switch (elf->ehdr.e_machine) {
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case EM_X86_64:
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return 1;
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case EM_386:
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return 0;
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default:
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WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
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return -1;
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}
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}
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bool arch_callee_saved_reg(unsigned char reg)
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{
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switch (reg) {
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case CFI_BP:
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case CFI_BX:
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case CFI_R12:
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case CFI_R13:
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case CFI_R14:
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case CFI_R15:
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return true;
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case CFI_AX:
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case CFI_CX:
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case CFI_DX:
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case CFI_SI:
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case CFI_DI:
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case CFI_SP:
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case CFI_R8:
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case CFI_R9:
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case CFI_R10:
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case CFI_R11:
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case CFI_RA:
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default:
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return false;
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}
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}
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int arch_decode_instruction(struct elf *elf, struct section *sec,
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unsigned long offset, unsigned int maxlen,
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unsigned int *len, unsigned char *type,
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unsigned long *immediate, struct stack_op *op)
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{
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struct insn insn;
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int x86_64, sign;
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unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
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rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
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modrm_reg = 0, sib = 0;
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x86_64 = is_x86_64(elf);
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if (x86_64 == -1)
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return -1;
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insn_init(&insn, sec->data->d_buf + offset, maxlen, x86_64);
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insn_get_length(&insn);
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if (!insn_complete(&insn)) {
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WARN_FUNC("can't decode instruction", sec, offset);
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return -1;
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}
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*len = insn.length;
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*type = INSN_OTHER;
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if (insn.vex_prefix.nbytes)
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return 0;
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op1 = insn.opcode.bytes[0];
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op2 = insn.opcode.bytes[1];
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if (insn.rex_prefix.nbytes) {
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rex = insn.rex_prefix.bytes[0];
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rex_w = X86_REX_W(rex) >> 3;
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rex_r = X86_REX_R(rex) >> 2;
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rex_x = X86_REX_X(rex) >> 1;
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rex_b = X86_REX_B(rex);
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}
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if (insn.modrm.nbytes) {
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modrm = insn.modrm.bytes[0];
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modrm_mod = X86_MODRM_MOD(modrm);
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modrm_reg = X86_MODRM_REG(modrm);
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modrm_rm = X86_MODRM_RM(modrm);
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}
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if (insn.sib.nbytes)
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sib = insn.sib.bytes[0];
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switch (op1) {
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case 0x1:
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case 0x29:
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if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
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/* add/sub reg, %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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break;
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case 0x50 ... 0x57:
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/* push reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
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op->dest.type = OP_DEST_PUSH;
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break;
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case 0x58 ... 0x5f:
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/* pop reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
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break;
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case 0x68:
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case 0x6a:
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/* push immediate */
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*type = INSN_STACK;
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op->src.type = OP_SRC_CONST;
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op->dest.type = OP_DEST_PUSH;
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break;
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case 0x70 ... 0x7f:
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*type = INSN_JUMP_CONDITIONAL;
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break;
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case 0x81:
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case 0x83:
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if (rex != 0x48)
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break;
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if (modrm == 0xe4) {
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/* and imm, %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_AND;
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op->src.reg = CFI_SP;
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op->src.offset = insn.immediate.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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if (modrm == 0xc4)
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sign = 1;
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else if (modrm == 0xec)
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sign = -1;
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else
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break;
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/* add/sub imm, %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = insn.immediate.value * sign;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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case 0x89:
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if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
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/* mov %rsp, reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
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break;
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}
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if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
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/* mov reg, %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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/* fallthrough */
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case 0x88:
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if (!rex_b &&
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(modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
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/* mov reg, disp(%rbp) */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_BP;
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op->dest.offset = insn.displacement.value;
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} else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
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/* mov reg, disp(%rsp) */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_SP;
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op->dest.offset = insn.displacement.value;
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}
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break;
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case 0x8b:
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if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
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/* mov disp(%rbp), reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_BP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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} else if (rex_w && !rex_b && sib == 0x24 &&
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modrm_mod != 3 && modrm_rm == 4) {
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/* mov disp(%rsp), reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_SP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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}
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break;
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case 0x8d:
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if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
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*type = INSN_STACK;
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if (!insn.displacement.value) {
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/* lea (%rsp), reg */
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op->src.type = OP_SRC_REG;
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} else {
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/* lea disp(%rsp), reg */
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op->src.type = OP_SRC_ADD;
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op->src.offset = insn.displacement.value;
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}
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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} else if (rex == 0x48 && modrm == 0x65) {
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/* lea disp(%rbp), %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_BP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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} else if (rex == 0x49 && modrm == 0x62 &&
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insn.displacement.value == -8) {
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/*
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* lea -0x8(%r10), %rsp
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*
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* Restoring rsp back to its original value after a
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* stack realignment.
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*/
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_R10;
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op->src.offset = -8;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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} else if (rex == 0x49 && modrm == 0x65 &&
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insn.displacement.value == -16) {
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/*
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* lea -0x10(%r13), %rsp
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*
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* Restoring rsp back to its original value after a
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* stack realignment.
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*/
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_R13;
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op->src.offset = -16;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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break;
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case 0x8f:
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/* pop to mem */
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*type = INSN_STACK;
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_MEM;
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break;
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case 0x90:
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*type = INSN_NOP;
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break;
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case 0x9c:
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/* pushf */
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*type = INSN_STACK;
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op->src.type = OP_SRC_CONST;
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op->dest.type = OP_DEST_PUSH;
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break;
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case 0x9d:
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/* popf */
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*type = INSN_STACK;
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_MEM;
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break;
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case 0x0f:
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if (op2 >= 0x80 && op2 <= 0x8f) {
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|
||
|
|
*type = INSN_JUMP_CONDITIONAL;
|
||
|
|
|
||
|
|
} else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
|
||
|
|
op2 == 0x35) {
|
||
|
|
|
||
|
|
/* sysenter, sysret */
|
||
|
|
*type = INSN_CONTEXT_SWITCH;
|
||
|
|
|
||
|
|
} else if (op2 == 0x0b || op2 == 0xb9) {
|
||
|
|
|
||
|
|
/* ud2 */
|
||
|
|
*type = INSN_BUG;
|
||
|
|
|
||
|
|
} else if (op2 == 0x0d || op2 == 0x1f) {
|
||
|
|
|
||
|
|
/* nopl/nopw */
|
||
|
|
*type = INSN_NOP;
|
||
|
|
|
||
|
|
} else if (op2 == 0xa0 || op2 == 0xa8) {
|
||
|
|
|
||
|
|
/* push fs/gs */
|
||
|
|
*type = INSN_STACK;
|
||
|
|
op->src.type = OP_SRC_CONST;
|
||
|
|
op->dest.type = OP_DEST_PUSH;
|
||
|
|
|
||
|
|
} else if (op2 == 0xa1 || op2 == 0xa9) {
|
||
|
|
|
||
|
|
/* pop fs/gs */
|
||
|
|
*type = INSN_STACK;
|
||
|
|
op->src.type = OP_SRC_POP;
|
||
|
|
op->dest.type = OP_DEST_MEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xc9:
|
||
|
|
/*
|
||
|
|
* leave
|
||
|
|
*
|
||
|
|
* equivalent to:
|
||
|
|
* mov bp, sp
|
||
|
|
* pop bp
|
||
|
|
*/
|
||
|
|
*type = INSN_STACK;
|
||
|
|
op->dest.type = OP_DEST_LEAVE;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xe3:
|
||
|
|
/* jecxz/jrcxz */
|
||
|
|
*type = INSN_JUMP_CONDITIONAL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xe9:
|
||
|
|
case 0xeb:
|
||
|
|
*type = INSN_JUMP_UNCONDITIONAL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xc2:
|
||
|
|
case 0xc3:
|
||
|
|
*type = INSN_RETURN;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xca: /* retf */
|
||
|
|
case 0xcb: /* retf */
|
||
|
|
case 0xcf: /* iret */
|
||
|
|
*type = INSN_CONTEXT_SWITCH;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xe8:
|
||
|
|
*type = INSN_CALL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0xff:
|
||
|
|
if (modrm_reg == 2 || modrm_reg == 3)
|
||
|
|
|
||
|
|
*type = INSN_CALL_DYNAMIC;
|
||
|
|
|
||
|
|
else if (modrm_reg == 4)
|
||
|
|
|
||
|
|
*type = INSN_JUMP_DYNAMIC;
|
||
|
|
|
||
|
|
else if (modrm_reg == 5)
|
||
|
|
|
||
|
|
/* jmpf */
|
||
|
|
*type = INSN_CONTEXT_SWITCH;
|
||
|
|
|
||
|
|
else if (modrm_reg == 6) {
|
||
|
|
|
||
|
|
/* push from mem */
|
||
|
|
*type = INSN_STACK;
|
||
|
|
op->src.type = OP_SRC_CONST;
|
||
|
|
op->dest.type = OP_DEST_PUSH;
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
*immediate = insn.immediate.nbytes ? insn.immediate.value : 0;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void arch_initial_func_cfi_state(struct cfi_state *state)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < CFI_NUM_REGS; i++) {
|
||
|
|
state->regs[i].base = CFI_UNDEFINED;
|
||
|
|
state->regs[i].offset = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initial CFA (call frame address) */
|
||
|
|
state->cfa.base = CFI_SP;
|
||
|
|
state->cfa.offset = 8;
|
||
|
|
|
||
|
|
/* initial RA (return address) */
|
||
|
|
state->regs[16].base = CFI_CFA;
|
||
|
|
state->regs[16].offset = -8;
|
||
|
|
}
|