61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
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/*
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* Copyright 2014, Michael Ellerman, IBM Corp.
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* Licensed under GPLv2.
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*/
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#ifndef _SELFTESTS_POWERPC_REG_H
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#define _SELFTESTS_POWERPC_REG_H
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#define __stringify_1(x) #x
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#define __stringify(x) __stringify_1(x)
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#define mfspr(rn) ({unsigned long rval; \
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asm volatile("mfspr %0," _str(rn) \
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: "=r" (rval)); rval; })
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#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
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: "r" ((unsigned long)(v)) \
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: "memory")
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#define mb() asm volatile("sync" : : : "memory");
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#define SPRN_MMCR2 769
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#define SPRN_MMCRA 770
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#define SPRN_MMCR0 779
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#define MMCR0_PMAO 0x00000080
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#define MMCR0_PMAE 0x04000000
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#define MMCR0_FC 0x80000000
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#define SPRN_EBBHR 804
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#define SPRN_EBBRR 805
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#define SPRN_BESCR 806 /* Branch event status & control register */
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#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
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#define SPRN_BESCRSU 801 /* Branch event status & control set upper */
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#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
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#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
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#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
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#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
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#define BESCR_LME (0x1ul << 34) /* Load Monitor Enable */
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#define BESCR_LMEO (0x1ul << 2) /* Load Monitor Exception Occurred */
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#define SPRN_LMRR 813 /* Load Monitor Region Register */
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#define SPRN_LMSER 814 /* Load Monitor Section Enable Register */
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#define SPRN_PMC1 771
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#define SPRN_PMC2 772
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#define SPRN_PMC3 773
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#define SPRN_PMC4 774
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#define SPRN_PMC5 775
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#define SPRN_PMC6 776
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#define SPRN_SIAR 780
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#define SPRN_SDAR 781
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#define SPRN_SIER 768
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#define SPRN_TEXASR 0x82
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#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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#define TEXASR_FS 0x08000000
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#define SPRN_TAR 0x32f
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#endif /* _SELFTESTS_POWERPC_REG_H */
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