47 lines
1.3 KiB
Plaintext
47 lines
1.3 KiB
Plaintext
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NVIDIA Carmel Uncore PMU
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========================
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This driver supports hardware perfmon event counting for the 4 L2 clusters
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and for the L3. The supported events are standard ARM L2/L3 event numbering,
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but shifted and masked with a unit number for the sake of granular unit
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tracking. The event format is EEU, where 'EE' is the standard ARM event number
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and U is the unit (0-3 for the L2s, 4 for the L3).
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These standard ARM events are supported:
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Event ID Type
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L2D_CACHE 0x16 L2
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L2D_CACHE_REFILL 0x17 L2
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L2D_CACHE_WB 0x18 L2
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BUS_ACCESS 0x19 L3
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BUS_CYCLES 0x1D L3
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L3D_CACHE_ALLOCATE 0x29 L3
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L3D_CACHE_REFILL 0x2A L3
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L3D_CACHE 0x2B L3
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L3D_CACHE_WB 0x2C L3
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L2D_CACHE_LD 0x50 L2
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L2D_CACHE_ST 0x51 L2
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L2D_CACHE_REFILL_LD 0x52 L2
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L2D_CACHE_REFILL_ST 0x53 L2
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L2D_CACHE_REFILL_VICTIM 0x56 L2
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For example, to track L2 cache events (0x16) on clusters 0 and 2 as well as L3
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events (0x2b):
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perf stat -a -e r160,r162,r2b4
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Required properties:
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- compatible : "nvidia,carmel-pmu"
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- interrupts : single hardware-specified interrupt
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- interrupt-affinity : this driver must be pinned to Carmel core 0 (cpu@0)
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in order to correctly field PMU interrupts from the L2/L3 units.
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Example:
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carmel-pmu {
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compatible = "nvidia,carmel-pmu";
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interrupts = <0 365 0x4>;
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interrupt-affinity = <&{/cpus/cpu@0}>;
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};
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