225 lines
9.4 KiB
Plaintext
225 lines
9.4 KiB
Plaintext
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Device tree binding for NVIDIA Tegra186 Ethernet QOS Controller
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=================================================================
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The Tegra186 EQOS (Ethernet QOS) device is an Ethernet controller which
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supports Quality of Service features.
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Supported Hardware Features are
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=====================================================/
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10/100 Mbps Support : YES
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1000 Mbps Support : YES
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Half-duplex Support : YES
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PCS Registers(TBI/SGMII/RTBI PHY interface) : NO
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VLAN Hash Filter Selected : NO
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SMA (MDIO) Interface : YES
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PMT Remote Wake-up Packet Enable : YES
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PMT Magic Packet Enable : YES
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RMON/MMC Module Enable : YES
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ARP Offload Enabled : YES
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IEEE 1588-2008 Timestamp Enabled : YES
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Energy Efficient Ethernet Enabled : YES
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Transmit Checksum Offload Enabled : YES
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Receive Checksum Offload Enabled : YES
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MAC Addresses 16–31 Selected : YES
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MAC Addresses 32–63 Selected : YES
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MAC Addresses 64–127 Selected : YES
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Timestamp System Time Source : INTERNAL
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Source Address or VLAN Insertion Enable : YES
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Active PHY Selected : RGMII
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MTL Receive FIFO Size : 16 KBytes
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MTL Transmit FIFO Size : 16 KBytes
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IEEE 1588 High Word Register Enable : YES
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DCB Feature Enable : NO
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Split Header Feature Enable : YES
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TCP Segmentation Offload Enable : YES
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DMA Debug Registers Enabled : YES
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AV Feature Enabled : YES
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Low Power Mode Enabled : YES
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Hash Table Size : No hash table selected
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Total number of L3 or L4 Filters : 8 L3/L4 Filter
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Number of MTL Receive Queues : 4
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Number of MTL Transmit Queues : 4
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Number of DMA Receive Channels : 4
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Number of DMA Transmit Channels : 4
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Number of PPS Outputs : No PPS output
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Number of Auxiliary Snapshot Inputs : 1 auxiliary input
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=====================================================/
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Required properties:
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- compatible: should be "nvidia,eqos"
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- reg: Physical base address and length of registers.
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- interrupts: An array of tuples specifying IRQ number for
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each tx/rx queue in case of multi-queue, and
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for the only tx/rx queue,in case of single queue.
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please check example at end for reference.
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- clocks: Specifies the needed clocks.
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- clock-names: Specifies the names of the needed clocks.
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- resets: Specifies the reset line.
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- reset-names: Specifies the name of the reset line.
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- iommu-group-id: Specifies IOMMU group ID.
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- nvidia,csr_clock_speed: This is a free-running clock input provided
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by the application. The MAC Control Interface,
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CSR, and Station Management Agent (SMA) of the
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MAC run on this clock. The valid frequency range
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of this clock is 20–300 MHz (minimum frequency
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is 25 MHz when the MMC module is active in
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1000 Mbps mode). Frequencies outside this range
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may result in incorrect operation
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- nvidia,use_multi_queues: EQOS HW supports upto 4 Tx/Rx Queues/Channels.
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This property enables us to make use of 4Queues,
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each queue size is configured to 4KB. if this
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property is not defined then EQOS HW is
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configured to make use of a single queue with a
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total of 16KB size.To support Jumbo frame
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feature we makes use of a single queue so that
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9k packet size can be fit into a single queue.
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- nvidia,ptp_ref_clock_speed: This is reference for PTP clock frequency and
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the value set for tegra is 125MHz.
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The frequency of this clock is programmable and
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can be configured based on the requirements.
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The maximum frequency it can take is 125MHz and
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minimum frequency is 25MHz
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- nvidia,queue_prio: An array where each entry specifies priority of
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rx queue. Based on the VLAN tag PCP priority
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value rx packets will be routed the corresponding
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channel.
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For example - If the values are "0 7 2 3", it
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means that packets with priority 0 will be
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mapped to DMA channel 0, similarly 7 will be
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mapped to 1 and so on.
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"nvidia,queue_prio = <0 7 2 3> " means
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priority-0 = DMA-0, priority-7 = DMA-1,
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priority-2 = DMA-2, priority-3 = DMA-3
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- nvidia,phy-reset-gpio: If this gpio is provided, then the PHY is reset
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by toggling this gpio LOW during driver probe.
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- nvidia,phy-intr-gpio: Specifies gpio pin for PHY interrupts.
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- nvidia,rxq_enable_ctrl: Mode of the RxQ to enabled either AV mode or legacy mode.
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example: rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
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0x0 = Not enabled, 0x1 = Enabled for AV
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0x2 = Enabled for Legacy, 0x3 = Reserved
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- nvidia,phy-max-frame-size: Specifies maximum frame size supported by PHY
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in kilobytes. Default is 10kb. It Will determine
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jumbo frame size.
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- phy-mode: should be "rgmii".
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- pinctrl-names If we define these property, then we can control
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EQOS pin-mux states dynamically so that we can
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save power based on the Ethernet link.
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- pinctrl-0 Valid only when "pinctrl-names" is defined, this
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property has the configuration that need to be
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set to EQOS signals when Ethernet link is down.
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- pinctrl-1 Valid only when "pinctrl-names" is defined, this
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property has the configuration that need to be
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set when Ethernet link is up.
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Optional properties:
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- nvidia,use_tagged_ptp: if this property is set we will make use of the
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channel/Queue which is defined in "ptp_dma_ch"
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for routing the rx ptp packets.
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- nvidia,ptp_dma_ch: Specifies channel/Queue number where the rx PTP
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packets need to be be routed.
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Channel 0 is default.
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- nvidia,chan_napi_quota: Specifies number of tx/rx completions to process
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when napi handler is called. Default is "64".
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- nvidia,pause_frames: Used to disable/enable PAUSE frames support.
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This is a flag. If this property is present
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then PAUSE frames will be enabled.
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- nvidia,brcm_phy_apd_mode: Flag specifies the Auto Power Down mode for
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BRCM89610 PHY.
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- nvidia,iso_bw: ISO BW, indicates sum of read and write bandwidth.
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- nvidia,eth_iso_enable: Specifies whether ISO enabled for EQOS or not.
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- nvidia,slot_intvl_val: Specifies slot interval for fetching the data from DMA.
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In T186 EQOS - 125usec is default and fixed value.
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In T194 EQOS this value can be changed based on the usecase.
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- nvidia,rx_riwt: Specifies the RX wathcdog interrupt timeout in usec
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for an Rx descriptor for which IOC bit is not set.
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The RIWT field is programmed as (<val> * 256) / 62.5
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- phy_rst_lp_mode Specifies that the phy should be put in reset for low
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power mode when it is set.
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Example:
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ether_qos@2490000 {
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compatible = "nvidia,eqos";
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reg = <0x0 0x02490000 0x0 0x10000>; /* EQOS Base Register */
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reg-names = "eqos_base";
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interrupts = <0 194 0x4>, /* common */
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<0 195 0x4>, /* power */
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<0 190 0x4>, /* rx0 */
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<0 186 0x4>, /* tx0 */
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<0 191 0x4>, /* rx1 */
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<0 187 0x4>, /* tx1 */
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<0 192 0x4>, /* rx2 */
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<0 188 0x4>, /* tx2 */
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<0 193 0x4>, /* rx3 */
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<0 189 0x4>; /* tx3 */
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nvidia,csr_clock_speed = <0x19>; /* CSR clock speed 25MHz */
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clocks = <&tegra_car TEGRA186_CLK_EQOS_AXI>,
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<&tegra_car TEGRA186_CLK_EQOS_RX>,
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<&tegra_car TEGRA186_CLK_EQOS_PTP_REF>,
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<&tegra_car TEGRA186_CLK_EQOS_TX>,
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<&tegra_car TEGRA186_CLK_AXI_CBB>;
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clock-names = "eqos_axi", "eqos_rx", "eqos_ptp_ref", "eqos_tx", "axi_cbb";
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resets = <&tegra_car TEGRA186_RESET_EQOS>;
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reset-names = "eqos_rst";
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phy-mode = "rgmii";
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status = "disabled";
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pinctrl-names = "idle", "default";
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pinctrl-0 = <&eqos_txrx_tri_state_idle>;
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pinctrl-1 = <&eqos_txrx_tri_state_default>;
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nvidia,queue_prio = <0 1 2 3>;
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nvidia,use_tagged_ptp;
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nvidia,chan_napi_quota = <64 64 64 64>;
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nvidia,ptp_dma_ch = <3>;
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nvidia,phy-max-frame-size = <10>;
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nvidia,ptp_ref_clock_speed = <125>;
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nvidia,use_multi_queues
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nvidia,brcm_phy_apd_mode;
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}
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Pinctrl Description (pinctrl-0/1 property)
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====================================================/
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The pinctrl property of the eqos node above manages the EQOS pin mux'ing and
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its configuration. In this case, enabling and disabling the pins drive state
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for the eqos function group.
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Proprties:
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- nvidia, pins Represent name of the pin or its mux group name.
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- nvidia, tristate pins are set to TEGRA_PIN_ENABLE in eqos idle state
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(eqos_idle) OR set to TEGRA_PIN_DISABLE in
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eqos active state (eqos_default)
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For more details on tegra pinmux controller and pins, please refer to
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the document nvidia,tegra186-pinmux.txt.
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Example:
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pinmux@2430000 {
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eqos_txrx_tri_state_idle: eqos_idle {
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eqos {
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nvidia,pins = "eqos_td3_pe4","eqos_td2_pe3",
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"eqos_td1_pe2","eqos_td0_pe1",
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"eqos_txc_pe0","eqos_tx_ctl_pe5",
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"eqos_rd3_pf1","eqos_rd2_pf0",
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"eqos_rd1_pe7","eqos_rd0_pe6",
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"eqos_rxc_pf3","eqos_rx_ctl_pf2";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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eqos_txrx_tri_state_default: eqos_default {
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eqos {
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nvidia,pins = "eqos_td3_pe4","eqos_td2_pe3",
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"eqos_td1_pe2","eqos_td0_pe1",
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"eqos_txc_pe0","eqos_tx_ctl_pe5",
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"eqos_rd3_pf1","eqos_rd2_pf0",
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"eqos_rd1_pe7","eqos_rd0_pe6",
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"eqos_rxc_pf3","eqos_rx_ctl_pf2";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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};
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}
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