57 lines
1.9 KiB
Plaintext
57 lines
1.9 KiB
Plaintext
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NVIDIA Tegra IVC channel bindings
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Each IVC channel represents the unique communication protocol defined
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between kernel running on CCPLEX CPUs and remote CPU core. Each IVC
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channel has two memory buffers, one for each direction. The RX buffer
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is for messages sent by the remote CPU, the TX channel for
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messages sent to the remote CPU.
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Both IPC memory buffers are have two headers followed by data
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frames. The first write header is updated only by the producer and the
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second read header is updated only by the consumer. The header and
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frame sizes are multiples of 64-byte cache lines.
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== IVC channel top-level node ==
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List of IVC channels implemented by remote core to talk to CCPLEX.
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The top-level node defines the AST region shared by IVC channels below
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it.
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Required properties:
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- #address-cells: Number of address cells in each subnode.
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Must be set to <1>.
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- #size-cells: Number of size cells in each subnode.
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Must be set to <0>.
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== IVC channel sub nodes ==
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Each IVC channel implemented by the remote CPU must be represented as
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a separate child node within the top-level node.
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Required properties:
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- compatible: Should represent the protocol to be used on this IVC channel.
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See other binding documents in this directory for potential values.
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For example:
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"nvidia,tegra186-ivc-protocol-echo" for ivc echo test channel.
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- reg: Address of the rx and tx buffers, respectively, inside the IVC region.
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Must be a multiple of 64.
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- nvidia,frame-size: Size of the data frame. Must be a multiple of 64.
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- nvidia,frame-count: Number of frames in rx or tx buffers.
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Optional properties:
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- reg-names: Names of the rx and tx buffers, respectively.
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Example:
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ivc-channels {
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#address-cells = <1>;
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#size-cells = <0>;
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echo@0 {
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compatible = "nvidia,tegra186-ivc-protocol-echo";
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reg = <0x0000>, <0x0480>;
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reg-names = "rx-echo", "tx-echo";
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nvidia,frame-size = <64>;
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nvidia,frame-count = <16>;
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};
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}
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