330 lines
8.2 KiB
C
330 lines
8.2 KiB
C
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/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/tick.h>
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#include <linux/vmalloc.h>
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#include <linux/syscore_ops.h>
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#include <linux/version.h>
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#define TMRCR 0x000
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#define TMRSR 0x004
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#define TMRCSSR 0x008
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#define TKEIE 0x100
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struct tegra186_tke;
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struct tegra186_tmr {
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struct clock_event_device evt;
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u64 tmr_index;
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u64 cpu_index;
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u32 freq;
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char name[20];
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void __iomem *reg_base;
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struct tegra186_tke *tke;
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};
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struct tegra186_tke {
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void __iomem *reg_base;
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struct tegra186_tmr tegra186_tmr[CONFIG_NR_CPUS];
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};
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static struct tegra186_tke *tke;
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static int tegra186_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct tegra186_tmr *tmr;
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tmr = container_of(evt, struct tegra186_tmr, evt);
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__raw_writel((1 << 31) /* EN=1, enable timer */
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| ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
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tmr->reg_base + TMRCR);
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return 0;
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}
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static inline void _shutdown(struct tegra186_tmr *tmr)
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{
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__raw_writel(0 << 31, /* EN=0, disable timer */
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tmr->reg_base + TMRCR);
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__raw_writel(1 << 30, /* INTR_CLR */
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tmr->reg_base + TMRSR);
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}
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static int tegra186_timer_shutdown(struct clock_event_device *evt)
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{
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struct tegra186_tmr *tmr;
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tmr = container_of(evt, struct tegra186_tmr, evt);
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_shutdown(tmr);
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return 0;
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}
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static int tegra186_timer_set_periodic(struct clock_event_device *evt)
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{
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struct tegra186_tmr *tmr = container_of(evt, struct tegra186_tmr, evt);
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_shutdown(tmr);
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__raw_writel((1 << 31) /* EN=1, enable timer */
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| (1 << 30) /* PER=1, periodic mode */
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| ((tmr->freq / HZ) - 1), /* PTV, preset value*/
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tmr->reg_base + TMRCR);
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return 0;
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)
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static void tegra186_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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tegra186_timer_set_periodic(evt);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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tegra186_timer_shutdown(evt);
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break;
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}
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}
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#endif
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static irqreturn_t tegra186_timer_isr(int irq, void *dev_id)
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{
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struct tegra186_tmr *tmr;
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tmr = (struct tegra186_tmr *) dev_id;
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__raw_writel(1 << 30, /* INTR_CLR */
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tmr->reg_base + TMRSR);
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tmr->evt.event_handler(&tmr->evt);
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return IRQ_HANDLED;
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}
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static int tegra186_timer_setup(unsigned int cpu)
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{
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struct tegra186_tmr *tmr = &tke->tegra186_tmr[cpu];
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clockevents_config_and_register(&tmr->evt, tmr->freq,
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1, /* min */
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0x1fffffff); /* 29 bits */
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#ifdef CONFIG_SMP
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if (irq_force_affinity(tmr->evt.irq, cpumask_of(cpu))) {
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pr_err("%s: cannot set irq %d affinity to CPU%d\n",
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__func__, tmr->evt.irq, cpu);
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BUG();
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}
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#endif
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enable_irq(tmr->evt.irq);
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return 0;
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}
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static int tegra186_timer_enable_irq(unsigned int cpu)
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{
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struct tegra186_tmr *tmr = &tke->tegra186_tmr[cpu];
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#ifdef CONFIG_SMP
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if (irq_force_affinity(tmr->evt.irq, cpumask_of(cpu))) {
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pr_err("%s: cannot set irq %d affinity to CPU%d\n",
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__func__, tmr->evt.irq, cpu);
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BUG();
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}
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#endif
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enable_irq(tmr->evt.irq);
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return 0;
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}
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static int tegra186_timer_stop(unsigned int cpu)
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{
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struct tegra186_tmr *tmr = &tke->tegra186_tmr[cpu];
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_shutdown(tmr);
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disable_irq_nosync(tmr->evt.irq);
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return 0;
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}
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static int tegra186_timer_suspend(void)
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{
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int cpu = smp_processor_id();
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struct tegra186_tmr *tmr = &tke->tegra186_tmr[cpu];
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_shutdown(tmr);
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disable_irq_nosync(tmr->evt.irq);
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return 0;
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
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static int tegra186_timer_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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tegra186_timer_setup(smp_processor_id());
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break;
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case CPU_DYING:
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tegra186_timer_stop(smp_processor_id());
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block tegra186_timer_cpu_nb = {
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.notifier_call = tegra186_timer_cpu_notify,
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};
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#endif
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static void tegra186_timer_resume(void)
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{
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int cpu;
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struct tegra186_tmr *tmr;
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for_each_possible_cpu(cpu) {
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tmr = &tke->tegra186_tmr[cpu];
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/* Configure TSC as the TKE source */
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__raw_writel(2, tmr->reg_base + TMRCSSR);
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__raw_writel(1 << tmr->tmr_index, tke->reg_base
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+ TKEIE + 4 * tmr->tmr_index);
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}
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cpu = smp_processor_id();
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tegra186_timer_enable_irq(cpu);
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}
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static struct syscore_ops tegra186_timer_syscore_ops = {
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.suspend = tegra186_timer_suspend,
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.resume = tegra186_timer_resume,
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};
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static void __init tegra186_timer_init(struct device_node *np)
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{
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int cpu;
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struct tegra186_tmr *tmr;
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u32 tmr_count;
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u32 freq;
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int irq_count;
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unsigned long tmr_index, irq_index;
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/* Allocate the driver struct */
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tke = vmalloc(sizeof(*tke));
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BUG_ON(!tke);
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memset(tke, 0, sizeof(*tke));
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/* MAp MMIO */
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tke->reg_base = of_iomap(np, 0);
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if (!tke->reg_base) {
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pr_err("%s: can't map timer registers\n", __func__);
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BUG();
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}
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/* Read the parameters */
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BUG_ON(of_property_read_u32(np, "tmr-count", &tmr_count));
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irq_count = of_irq_count(np);
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BUG_ON(of_property_read_u32(np, "clock-frequency", &freq));
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tmr_index = 0;
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for_each_possible_cpu(cpu) {
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tmr = &tke->tegra186_tmr[cpu];
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tmr->tke = tke;
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tmr->tmr_index = tmr_index;
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tmr->freq = freq;
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/* Allocate a TMR */
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BUG_ON(tmr_index >= tmr_count);
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tmr->reg_base = tke->reg_base + 0x10000 * (tmr_index + 1);
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/* Allocate an IRQ */
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irq_index = tmr_index;
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BUG_ON(irq_index >= irq_count);
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/* Program TKEIE to map TMR to the right IRQ */
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__raw_writel(1 << tmr_index, tke->reg_base
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+ TKEIE + 4 * irq_index);
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tmr->evt.irq = irq_of_parse_and_map(np, irq_index);
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BUG_ON(!tmr->evt.irq);
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/* Configure OSC as the TKE source */
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__raw_writel(1, tmr->reg_base + TMRCSSR);
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snprintf(tmr->name, sizeof(tmr->name), "tegra186_timer%d", cpu);
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tmr->evt.name = tmr->name;
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tmr->evt.cpumask = cpumask_of(cpu);
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tmr->evt.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT;
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tmr->evt.set_next_event = tegra186_timer_set_next_event;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)
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tmr->evt.set_mode = tegra186_timer_set_mode;
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#else
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tmr->evt.set_state_shutdown = tegra186_timer_shutdown;
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tmr->evt.set_state_periodic = tegra186_timer_set_periodic;
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tmr->evt.set_state_oneshot = tegra186_timer_shutdown;
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tmr->evt.tick_resume = tegra186_timer_shutdown;
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#endif
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/* want to be preferred over arch timers */
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tmr->evt.rating = 460;
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irq_set_status_flags(tmr->evt.irq, IRQ_NOAUTOEN | IRQ_PER_CPU);
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if (request_irq(tmr->evt.irq, tegra186_timer_isr,
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IRQF_TIMER | IRQF_TRIGGER_HIGH
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| IRQF_NOBALANCING, tmr->name, tmr)) {
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pr_err("%s: cannot setup irq %d for CPU%d\n",
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__func__, tmr->evt.irq, cpu);
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BUG();
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}
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tmr_index++;
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
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/* boot cpu is online */
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tegra186_timer_setup(0);
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if (register_cpu_notifier(&tegra186_timer_cpu_nb)) {
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pr_err("%s: cannot setup CPU notifier\n", __func__);
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BUG();
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}
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#else
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cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
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"AP_TEGRA_TIMER_STARTING", tegra186_timer_setup,
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tegra186_timer_stop);
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#endif
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register_syscore_ops(&tegra186_timer_syscore_ops);
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
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#define tegra186_timer_init_func tegra186_timer_init
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#else
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static int __init tegra186_timer_init_ret(struct device_node *np)
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{
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tegra186_timer_init(np);
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return 0;
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}
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#define tegra186_timer_init_func tegra186_timer_init_ret
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#endif
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CLOCKSOURCE_OF_DECLARE(tegra186_timer, "nvidia,tegra186-timer",
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tegra186_timer_init_func);
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