192 lines
8.4 KiB
C
192 lines
8.4 KiB
C
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/*
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* SDIO device core hardware definitions.
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* sdio is a portion of the pcmcia core in core rev 3 - rev 8
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*
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* SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
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*
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* Portions of this code are copyright (c) 2017 Cypress Semiconductor Corporation
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: sbsdio.h 514727 2014-11-12 03:02:48Z $
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*/
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#ifndef _SBSDIO_H
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#define _SBSDIO_H
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#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
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/* function 1 miscellaneous registers */
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#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
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#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
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#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
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#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
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#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
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#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
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#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
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#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
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#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
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#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
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/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
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#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
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#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
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#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
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#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
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#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
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#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
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#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
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#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
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#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
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#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
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#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D /* MesBusyCtl at 0x1001D (rev 11) */
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#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
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#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
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/* Sdio Core Rev 12 */
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#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
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#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
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/* SBSDIO_SPROM_CS */
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#define SBSDIO_SPROM_IDLE 0
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#define SBSDIO_SPROM_WRITE 1
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#define SBSDIO_SPROM_READ 2
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#define SBSDIO_SPROM_WEN 4
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#define SBSDIO_SPROM_WDS 7
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#define SBSDIO_SPROM_DONE 8
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/* SBSDIO_SPROM_INFO */
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#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
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#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
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#define SROM_OTP 0x80 /* OTP present */
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/* SBSDIO_CHIP_CTRL */
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#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
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* 1: power on oscillator
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* (for 4318 only)
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*/
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/* SBSDIO_WATERMARK */
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#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
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* to wait before sending data to host
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*/
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/* SBSDIO_MESBUSYCTRL */
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/* When RX FIFO has less entries than this & MBE is set
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* => busy signal is asserted between data blocks.
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*/
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#define SBSDIO_MESBUSYCTRL_MASK 0x7f
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#define SBSDIO_MESBUSYCTRL_ENAB 0x80 /* Enable busy capability for MES access */
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/* SBSDIO_DEVICE_CTL */
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#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
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* receiving CMD53
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*/
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#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
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* synchronous to the sdio clock
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*/
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#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
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* except the chipActive (rev 8)
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*/
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#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
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* external pads in tri-state; requires
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* sdio bus power cycle to clear (rev 9)
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*/
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#define SBSDIO_DEVCTL_EN_F2_BLK_WATERMARK 0x10 /* Enable function 2 tx for each block */
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#define SBSDIO_DEVCTL_F2WM_ENAB 0x10 /* Enable F2 Watermark */
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#define SBSDIO_DEVCTL_NONDAT_PADS_ISO 0x20 /* Isolate sdio clk and cmd (non-data) */
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/* SBSDIO_FUNC1_CHIPCLKCSR */
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#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
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#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
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#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
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#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
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#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
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#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
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#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
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#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
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/* In rev8, actual avail bits followed original docs */
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#define SBSDIO_Rev8_HT_AVAIL 0x40
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#define SBSDIO_Rev8_ALP_AVAIL 0x80
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#define SBSDIO_CSR_MASK 0x1F
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#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
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#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
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#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
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#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
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#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
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(alponly ? 1 : SBSDIO_HTAV(regval)))
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/* SBSDIO_FUNC1_SDIOPULLUP */
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#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
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#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
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#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
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#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
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#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
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/* function 1 OCP space */
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#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
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#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
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#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
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/* some duplication with sbsdpcmdev.h here */
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/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
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#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
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#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
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#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
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#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
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/* direct(mapped) cis space */
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#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
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#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
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#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
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#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
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#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
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* link bytes
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*/
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/* indirect cis access (in sprom) */
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#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
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* 8th byte
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*/
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#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
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* data comamnd
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*/
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#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
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#endif /* _SBSDIO_H */
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