257 lines
6.3 KiB
C
257 lines
6.3 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __INC_HAL8188EPHYCFG_H__
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#define __INC_HAL8188EPHYCFG_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 /* us */
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#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#ifdef CONFIG_PCI_HCI
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#define MAX_AGGR_NUM 0x0B
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#else
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#define MAX_AGGR_NUM 0x07
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#endif /* CONFIG_PCI_HCI */
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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#define MAX_TX_COUNT_8188E 1
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/* BB/RF related */
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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/*
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* BB and RF register read/write
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* */
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u32 PHY_QueryBBReg8188E(PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask);
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void PHY_SetBBReg8188E(PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask,
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u32 Data);
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u32 PHY_QueryRFReg8188E(PADAPTER Adapter,
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enum rf_path eRFPath,
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u32 RegAddr,
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u32 BitMask);
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void PHY_SetRFReg8188E(PADAPTER Adapter,
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enum rf_path eRFPath,
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u32 RegAddr,
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u32 BitMask,
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u32 Data);
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/*
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* Initialization related function
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*/
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8188E(PADAPTER Adapter);
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int PHY_BBConfig8188E(PADAPTER Adapter);
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int PHY_RFConfig8188E(PADAPTER Adapter);
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/* RF config */
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int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);
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/*
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* RF Power setting
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*/
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/* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter,
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* RT_RF_POWER_STATE eRFPowerState); */
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/*
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* BB TX Power R/W
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* */
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void PHY_SetTxPowerLevel8188E(PADAPTER Adapter,
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u8 channel);
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void
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PHY_SetTxPowerIndex_8188E(
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PADAPTER Adapter,
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u32 PowerIndex,
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enum rf_path RFPath,
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u8 Rate
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);
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u8
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PHY_GetTxPowerIndex_8188E(
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PADAPTER pAdapter,
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enum rf_path RFPath,
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u8 Rate,
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u8 BandWidth,
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u8 Channel,
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struct txpwr_idx_comp *tic
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);
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/*
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* Switch bandwidth for 8192S
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*/
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/* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */
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void PHY_SetBWMode8188E(PADAPTER pAdapter,
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enum channel_width ChnlWidth,
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unsigned char Offset);
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/*
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* Set FW CMD IO for 8192S.
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*/
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/* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter,
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* IO_TYPE IOType); */
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/*
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* Set A2 entry to fw for 8192S
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* */
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extern void FillA2Entry8192C(PADAPTER Adapter,
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u8 index,
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u8 *val);
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/*
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* channel switch related funciton
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*/
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/* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */
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void PHY_SwChnl8188E(PADAPTER pAdapter,
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u8 channel);
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void
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PHY_SetSwChnlBWMode8188E(
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PADAPTER Adapter,
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u8 channel,
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enum channel_width Bandwidth,
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u8 Offset40,
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u8 Offset80
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);
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void
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PHY_SetRFEReg_8188E(
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PADAPTER Adapter
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);
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/*
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* BB/MAC/RF other monitor API
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* */
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void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain);
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extern void
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PHY_SwitchEphyParameter(
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PADAPTER Adapter
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);
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extern void
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PHY_EnableHostClkReq(
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PADAPTER Adapter
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);
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BOOLEAN
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SetAntennaConfig92C(
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PADAPTER Adapter,
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u8 DefaultAnt
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);
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/*--------------------------Exported Function prototype---------------------*/
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/*
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* Initialization related function
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*
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* MAC/BB/RF HAL config */
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/* extern s32 PHY_MACConfig8723(PADAPTER padapter);
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* s32 PHY_BBConfig8723(PADAPTER padapter);
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* s32 PHY_RFConfig8723(PADAPTER padapter); */
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/* ******************************************************************
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* Note: If SIC_ENABLE under PCIE, because of the slow operation
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* you should
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* 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
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* 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
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* */
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#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
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#define SIC_ENABLE 1
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#define SIC_HW_SUPPORT 1
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#else
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#define SIC_ENABLE 0
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#define SIC_HW_SUPPORT 0
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#endif
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/* ****************************************************************** */
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#define SIC_MAX_POLL_CNT 5
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#if (SIC_HW_SUPPORT == 1)
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#define SIC_CMD_READY 0
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#define SIC_CMD_PREWRITE 0x1
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#if (RTL8188E_SUPPORT == 1)
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#define SIC_CMD_WRITE 0x40
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#define SIC_CMD_PREREAD 0x2
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#define SIC_CMD_READ 0x80
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#define SIC_CMD_INIT 0xf0
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#define SIC_INIT_VAL 0xff
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#define SIC_INIT_REG 0x1b7
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1b0~1b3 */
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#else
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#define SIC_CMD_WRITE 0x11
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#define SIC_CMD_PREREAD 0x2
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#define SIC_CMD_READ 0x12
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#define SIC_CMD_INIT 0x1f
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#define SIC_INIT_VAL 0xff
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#define SIC_INIT_REG 0x1b7
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#define SIC_CMD_REG 0x1b6 /* 1byte */
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#define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */
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#define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */
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#endif
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#else
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#define SIC_CMD_READY 0
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#define SIC_CMD_WRITE 1
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#define SIC_CMD_READ 2
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#if (RTL8188E_SUPPORT == 1)
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1bc~1bf */
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#else
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#define SIC_CMD_REG 0x1b8 /* 1byte */
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#define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1bc /* 1bc~1bf */
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#endif
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#endif
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#if (SIC_ENABLE == 1)
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void SIC_Init( PADAPTER Adapter);
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#endif
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#endif /* __INC_HAL8192CPHYCFG_H */
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