313 lines
10 KiB
C
313 lines
10 KiB
C
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/*
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* t19x-nvlink-endpt.h:
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* This header contains the structures and APIs needed by the Tegra NVLINK
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* endpoint driver.
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef T19X_NVLINK_ENDPT_H
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#define T19X_NVLINK_ENDPT_H
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/interrupt.h>
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#include <linux/of_graph.h>
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/module.h>
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#include <linux/platform/tegra/mc.h>
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#include <linux/platform/tegra/mc-regs-t19x.h>
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#include <linux/tegra_prod.h>
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#include <linux/device.h>
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#include <linux/cdev.h>
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#include <linux/platform/tegra/tegra-nvlink.h>
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#define NVLINK_MODULE_NAME "t19x-nvlink-endpt"
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#define NVLINK_IP_VERSION 2 /* NVLINK VERSION 2.0 */
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#define DEFAULT_IS_NEA 0
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enum nvlink_refclk {
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NVLINK_REFCLK_150,
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NVLINK_REFCLK_156
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};
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/* Struct used for passing around error masks in error handling functions */
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struct nvlink_link_error_masks {
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u32 dl;
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u32 tl;
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u32 tl_injected;
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u32 tlc_rx0;
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u32 tlc_rx0_injected;
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u32 tlc_rx1;
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u32 tlc_rx1_injected;
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u32 tlc_tx;
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u32 tlc_tx_injected;
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};
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/* Fatal Errors */
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enum inforom_nvlink_fatal_err {
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/* NVLink 2.0 */
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TLC_RX_DL_DATA_PARITY,
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TLC_RX_DL_CTRL_PARITY,
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TLC_RX_RAM_DATA_PARITY,
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TLC_RX_RAM_HDR_PARITY,
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TLC_RX_DATA_POISONED_PKT_RCVD,
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TLC_TX_RAM_DATA_PARITY,
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TLC_TX_RAM_HDR_PARITY,
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TLC_TX_DL_FLOW_CONTROL_PARITY,
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DL_TX_RECOVERY_LONG,
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DL_TX_FAULT_RAM,
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DL_TX_FAULT_INTERFACE,
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DL_TX_FAULT_SUBLINK_CHANGE,
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DL_RX_FAULT_SUBLINK_CHANGE,
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DL_RX_FAULT_DL_PROTOCOL,
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DL_LTSSM_FAULT,
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TLC_RX_DL_HDR_PARITY,
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TLC_RX_INVALID_AE_FLIT_RCVD,
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TLC_RX_INVALID_BE_FLIT_RCVD,
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TLC_RX_INVALID_ADDR_ALIGN,
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TLC_RX_PKT_LEN,
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TLC_RX_RSVD_CMD_ENC,
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TLC_RX_RSVD_DAT_LEN_ENC,
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TLC_RX_RSVD_ADDR_TYPE,
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TLC_RX_RSVD_RSP_STATUS,
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TLC_RX_RSVD_PKT_STATUS,
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TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ,
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TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP,
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TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE,
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TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE,
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TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE,
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TLC_RX_INVALID_PO_FOR_CACHE_ATTR,
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TLC_RX_INVALID_COMPRESSED_RESP,
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TLC_RX_RESP_STATUS_TARGET,
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TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST,
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TLC_RX_HDR_OVERFLOW,
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TLC_RX_DATA_OVERFLOW,
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TLC_RX_STOMPED_PKT_RCVD,
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TLC_RX_CORRECTABLE_INTERNAL,
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TLC_RX_UNSUPPORTED_VC_OVERFLOW,
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TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE,
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TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE,
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TLC_TX_HDR_CREDIT_OVERFLOW,
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TLC_TX_DATA_CREDIT_OVERFLOW,
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TLC_TX_DL_REPLAY_CREDIT_OVERFLOW,
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TLC_TX_UNSUPPORTED_VC_OVERFLOW,
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TLC_TX_STOMPED_PKT_SENT,
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TLC_TX_DATA_POISONED_PKT_SENT,
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TLC_TX_RESP_STATUS_TARGET,
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TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST,
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};
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/*
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* This structure is used for storing parameters which describe the Single-Lane
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* (SL / 1/8th) mode policy. A few acronyms that are used in this structure are
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* as follows:
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* - SL = Single-Lane / 1/8th mode - sublink low power mode where only 1 of
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* the 8 lanes is used
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* - FB = Full Bandwidth (i.e. HISPEED mode)
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* - LP = Low Power (i.e. SL / 1/8th mode)
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* - IC = Idle Counter - the idle counter is used to monitor traffic per
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* sub-link
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*/
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struct single_lane_params {
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/* Idle counter increment in FB */
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u16 fb_ic_inc;
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/* Idle counter increment in LP */
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u16 lp_ic_inc;
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/* Idle counter decrement in FB */
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u16 fb_ic_dec;
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/* Idle counter decrement in LP */
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u16 lp_ic_dec;
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/* SL entry threshold */
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u32 enter_thresh;
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/* SL exit threshold */
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u32 exit_thresh;
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/* Idle counter saturation limit */
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u32 ic_limit;
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};
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/* Tegra endpoint driver's private link struct */
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struct tnvlink_link {
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/* base address of DLPL */
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void __iomem *nvlw_nvl_base;
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/* base address of TL */
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void __iomem *nvlw_nvltlc_base;
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/* TLC errors status. TODO: Add more description here */
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u32 tlc_tx_err_status0;
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u32 tlc_rx_err_status0;
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u32 tlc_rx_err_status1;
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/* Successful error recoveries */
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u32 error_recoveries;
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/* Parameters which describe the selected Single-Lane policy */
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struct single_lane_params sl_params;
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/* Pointer to parent struct tnvlink_dev */
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struct tnvlink_dev *tdev;
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/* Pointer to parent struct nvlink_link */
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struct nvlink_link *nlink;
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};
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/* Tegra endpoint driver's private device struct */
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struct tnvlink_dev {
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/* Are we using the RM shim driver? */
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bool rm_shim_enabled;
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/* base address of minion */
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void __iomem *nvlw_minion_base;
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/* base address of IOCTRL */
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void __iomem *nvlw_tioctrl_base;
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/* base address of NVLIPT */
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void __iomem *nvlw_nvlipt_base;
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/* base address of SYNC2X */
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void __iomem *nvlw_sync2x_base;
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/* base address of MSSNVLINK */
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void __iomem *mssnvlink_0_base;
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/* irq below represents the interrupt line going to GIC and LIC */
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int irq;
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struct class class;
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dev_t dev_t;
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struct cdev cdev;
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struct device *dev;
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#ifdef CONFIG_DEBUG_FS
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/* This is the debugfs directory for the Tegra endpoint driver */
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struct dentry *tegra_debugfs;
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struct dentry *tegra_debugfs_file;
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#endif /* CONFIG_DEBUG_FS */
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/* clocks */
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struct clk *clk_nvhs_pll0_mgmt;
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struct clk *clk_pllrefe_vcoout_gated;
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struct clk *clk_nvlink_sys;
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struct clk *clk_pllnvhs;
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struct clk *clk_m;
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struct clk *clk_nvlink_pll_txclk;
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struct clk *clk_nvlink_tx;
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/* resets */
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struct reset_control *rst_mssnvl;
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struct reset_control *rst_nvhs_uphy_pm;
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struct reset_control *rst_nvhs_uphy;
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struct reset_control *rst_nvhs_uphy_pll0;
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struct reset_control *rst_nvhs_uphy_l0;
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struct reset_control *rst_nvhs_uphy_l1;
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struct reset_control *rst_nvhs_uphy_l2;
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struct reset_control *rst_nvhs_uphy_l3;
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struct reset_control *rst_nvhs_uphy_l4;
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struct reset_control *rst_nvhs_uphy_l5;
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struct reset_control *rst_nvhs_uphy_l6;
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struct reset_control *rst_nvhs_uphy_l7;
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struct reset_control *rst_nvlink;
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struct tegra_prod *prod_list;
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bool is_nea;
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/* Nvlink refclk*/
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enum nvlink_refclk refclk;
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bool is_tp_cntr_running;
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struct tnvlink_link tlink;
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struct nvlink_device *ndev;
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};
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extern const struct single_lane_params entry_100us_sl_params;
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extern const struct file_operations t19x_nvlink_endpt_ops;
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u32 nvlw_tioctrl_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_tioctrl_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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u32 nvlw_nvlipt_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_nvlipt_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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u32 nvlw_minion_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_minion_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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u32 nvlw_nvl_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_nvl_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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u32 nvlw_sync2x_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_sync2x_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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u32 nvlw_nvltlc_readl(struct tnvlink_dev *tdev, u32 reg);
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void nvlw_nvltlc_writel(struct tnvlink_dev *tdev, u32 reg, u32 val);
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int t19x_nvlink_dev_car_disable(struct nvlink_device *ndev);
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int t19x_nvlink_suspend(struct device *dev);
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int wait_for_reg_cond_nvlink(
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struct tnvlink_dev *tdev,
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u32 reg,
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u32 bit,
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bool check_for_bit_set,
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char *bit_name,
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u32 (*reg_readl)(struct tnvlink_dev *, u32),
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u32 *reg_val,
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u32 timeout_us);
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int t19x_nvlink_dev_interface_disable(struct nvlink_device *ndev);
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void minion_dump_pc_trace(struct tnvlink_dev *tdev);
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void minion_dump_registers(struct tnvlink_dev *tdev);
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int minion_boot(struct tnvlink_dev *tdev);
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int init_nvhs_phy(struct tnvlink_dev *tdev);
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int minion_send_cmd(struct tnvlink_dev *tdev,
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u32 cmd,
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u32 scratch0_val);
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void nvlink_enable_AN0_packets(struct tnvlink_dev *tdev);
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void nvlink_config_minion_falcon_intr(struct tnvlink_dev *tdev);
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void nvlink_config_common_intr(struct tnvlink_dev *tdev);
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void nvlink_enable_dl_interrupts(struct tnvlink_dev *tdev);
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void nvlink_enable_link_interrupts(struct tnvlink_dev *tdev);
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void nvlink_disable_link_interrupts(struct tnvlink_dev *tdev);
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void minion_service_falcon_intr(struct tnvlink_dev *tdev);
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void nvlink_disable_dl_interrupts(struct tnvlink_dev *tdev);
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int nvlink_service_dl_interrupts(struct tnvlink_dev *tdev,
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bool *retrain_from_safe);
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irqreturn_t t19x_nvlink_endpt_isr(int irq, void *dev_id);
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void init_single_lane_params(struct tnvlink_dev *tdev);
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u32 t19x_nvlink_get_link_state(struct nvlink_device *ndev);
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u32 t19x_nvlink_get_link_mode(struct nvlink_device *ndev);
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int t19x_nvlink_set_link_mode(struct nvlink_device *ndev, u32 mode);
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void t19x_nvlink_get_tx_sublink_state(struct nvlink_device *ndev,
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u32 *tx_sublink_state);
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void t19x_nvlink_get_rx_sublink_state(struct nvlink_device *ndev,
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u32 *rx_sublink_state);
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u32 t19x_nvlink_get_sublink_mode(struct nvlink_device *ndev,
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bool is_rx_sublink);
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int t19x_nvlink_set_sublink_mode(struct nvlink_device *ndev, bool is_rx_sublink,
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u32 mode);
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bool is_link_connected(struct tnvlink_link *tlink);
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int nvlink_retrain_link(struct tnvlink_dev *tdev, bool from_off);
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int t19x_nvlink_write_discovery_token(struct tnvlink_dev *tdev, u64 token);
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int t19x_nvlink_read_discovery_token(struct tnvlink_dev *tdev, u64 *token);
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int t19x_nvlink_reset_tp_counters(struct tnvlink_dev *tdev);
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int t19x_nvlink_freeze_tp_counters(struct tnvlink_dev *tdev, bool bFreeze);
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int t19x_nvlink_config_tp_counters(struct tnvlink_dev *tdev);
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int t19x_nvlink_get_tp_counters(struct tnvlink_dev *tdev, u64 *tx0cnt,
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u64 *tx1cnt, u64 *rx0cnt, u64 *rx1cnt);
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#ifdef CONFIG_DEBUG_FS
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void t19x_nvlink_endpt_debugfs_init(struct tnvlink_dev *tdev);
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void t19x_nvlink_endpt_debugfs_deinit(struct tnvlink_dev *tdev);
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#else
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static inline void t19x_nvlink_endpt_debugfs_init(struct tnvlink_dev *tdev) {}
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static inline void t19x_nvlink_endpt_debugfs_deinit(
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struct tnvlink_dev *tdev) {}
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#endif /* CONFIG_DEBUG_FS */
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#endif /* T19X_NVLINK_ENDPT_H */
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