505 lines
14 KiB
C
505 lines
14 KiB
C
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/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Suresh Mangipudi <smangipudi@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/reset.h>
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#include <linux/tegra-powergate.h>
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#include <dt-bindings/soc/tegra186-powergate.h>
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#include <dt-bindings/soc/tegra194-powergate.h>
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#include "core.h"
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#include "pinctrl-utils.h"
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#define DPAUX_HYBRID_PADCTL 0x124
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#define I2C_SDA_INPUT BIT(15)
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#define I2C_SCL_INPUT BIT(14)
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#define MODE BIT(0)
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#define DPAUX_HYBRID_SPARE 0x134
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#define PAD_PWR BIT(0)
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struct tegra_dpaux_function {
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const char *name;
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const char * const *groups;
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unsigned int ngroups;
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};
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struct tegra_dpaux_pingroup {
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const char *name;
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const unsigned int pins[1];
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u8 npins;
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u8 funcs[2];
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};
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struct dpaux_context {
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u32 val_padctl;
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u32 val_spare;
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};
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struct tegra_dpaux_pinctl {
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struct device *dev;
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void __iomem *regs;
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struct platform_device *pdev;
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struct pinctrl_desc desc;
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struct pinctrl_dev *pinctrl;
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const struct pinctrl_pin_desc *pins;
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unsigned npins;
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const struct tegra_dpaux_function *functions;
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unsigned int nfunctions;
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const struct tegra_dpaux_pingroup *groups;
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unsigned ngroups;
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int powergate_id;
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struct clk *dpaux_clk;
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struct dpaux_context dpaux_context;
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};
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struct tegra_dpaux_chip_data {
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const struct pinctrl_pin_desc *pins;
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u32 npins;
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const struct tegra_dpaux_pingroup *pin_group;
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u32 npin_groups;
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struct tegra_dpaux_function *functions;
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u32 nfunctions;
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int powergate_id;
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};
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#define TEGRA_PIN_DPAUX_0 0
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#define TEGRA_PIN_DPAUX1_1 1
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#define TEGRA_PIN_DPAUX2_2 2
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#define TEGRA_PIN_DPAUX3_3 3
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static const struct pinctrl_pin_desc tegra186_dpaux_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_DPAUX_0, "dpaux-0"),
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PINCTRL_PIN(TEGRA_PIN_DPAUX1_1, "dpaux1-1"),
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};
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static const struct pinctrl_pin_desc tegra194_dpaux_pins[] = {
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PINCTRL_PIN(TEGRA_PIN_DPAUX_0, "dpaux-0"),
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PINCTRL_PIN(TEGRA_PIN_DPAUX1_1, "dpaux1-1"),
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PINCTRL_PIN(TEGRA_PIN_DPAUX2_2, "dpaux2-2"),
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PINCTRL_PIN(TEGRA_PIN_DPAUX3_3, "dpaux3-3"),
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};
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enum tegra_dpaux_mux {
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TEGRA_DPAUX_MUX_I2C,
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TEGRA_DPAUX_MUX_DISPLAY,
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};
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#define TEGRA186_PIN_NAMES "dpaux-0", "dpaux1-1"
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static const char * const tegra186_dpaux_pin_groups[] = {
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TEGRA186_PIN_NAMES
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};
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#define TEGRA194_PIN_NAMES "dpaux-0", "dpaux1-1", "dpaux2-2", "dpaux3-3"
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static const char * const tegra194_dpaux_pin_groups[] = {
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TEGRA194_PIN_NAMES
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};
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#define FUNCTION(fname, group) \
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{ \
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.name = #fname, \
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.groups = group, \
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.ngroups = ARRAY_SIZE(group), \
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} \
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static struct tegra_dpaux_function tegra186_dpaux_functions[] = {
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FUNCTION(i2c, tegra186_dpaux_pin_groups),
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FUNCTION(display, tegra186_dpaux_pin_groups),
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};
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static struct tegra_dpaux_function tegra194_dpaux_functions[] = {
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FUNCTION(i2c, tegra194_dpaux_pin_groups),
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FUNCTION(display, tegra194_dpaux_pin_groups),
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};
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#define PINGROUP(pg_name, pin_id, f0, f1) \
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{ \
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.name = #pg_name, \
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.pins = {TEGRA_PIN_##pin_id}, \
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.npins = 1, \
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.funcs = { \
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TEGRA_DPAUX_MUX_##f0, \
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TEGRA_DPAUX_MUX_##f1, \
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}, \
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}
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static const struct tegra_dpaux_pingroup tegra186_dpaux_groups[] = {
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PINGROUP(dpaux_0, DPAUX_0, I2C, DISPLAY),
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PINGROUP(dpaux1_1, DPAUX1_1, I2C, DISPLAY),
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};
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static const struct tegra_dpaux_pingroup tegra194_dpaux_groups[] = {
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PINGROUP(dpaux_0, DPAUX_0, I2C, DISPLAY),
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PINGROUP(dpaux1_1, DPAUX1_1, I2C, DISPLAY),
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PINGROUP(dpaux2_2, DPAUX2_2, I2C, DISPLAY),
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PINGROUP(dpaux3_3, DPAUX3_3, I2C, DISPLAY),
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};
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static struct tegra_dpaux_chip_data tegra186_dpaux_chip_data[] = {
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{
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.pins = tegra186_dpaux_pins,
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.npins = ARRAY_SIZE(tegra186_dpaux_pins),
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.pin_group = tegra186_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra186_dpaux_groups),
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.functions = tegra186_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra186_dpaux_functions),
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.powergate_id = TEGRA186_POWER_DOMAIN_DISP,
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},
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{
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.pins = tegra186_dpaux_pins,
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.npins = ARRAY_SIZE(tegra186_dpaux_pins),
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.pin_group = tegra186_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra186_dpaux_groups),
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.functions = tegra186_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra186_dpaux_functions),
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.powergate_id = TEGRA186_POWER_DOMAIN_DISP,
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},
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};
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static struct tegra_dpaux_chip_data tegra194_dpaux_chip_data[] = {
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{
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.pins = tegra194_dpaux_pins,
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.npins = ARRAY_SIZE(tegra194_dpaux_pins),
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.pin_group = tegra194_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra194_dpaux_groups),
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.functions = tegra194_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra194_dpaux_functions),
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.powergate_id = TEGRA194_POWER_DOMAIN_DISP,
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},
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{
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.pins = tegra194_dpaux_pins,
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.npins = ARRAY_SIZE(tegra194_dpaux_pins),
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.pin_group = tegra194_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra194_dpaux_groups),
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.functions = tegra194_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra194_dpaux_functions),
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.powergate_id = TEGRA194_POWER_DOMAIN_DISP,
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},
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{
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.pins = tegra194_dpaux_pins,
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.npins = ARRAY_SIZE(tegra194_dpaux_pins),
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.pin_group = tegra194_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra194_dpaux_groups),
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.functions = tegra194_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra194_dpaux_functions),
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.powergate_id = TEGRA194_POWER_DOMAIN_DISP,
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},
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{
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.pins = tegra194_dpaux_pins,
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.npins = ARRAY_SIZE(tegra194_dpaux_pins),
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.pin_group = tegra194_dpaux_groups,
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.npin_groups = ARRAY_SIZE(tegra194_dpaux_groups),
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.functions = tegra194_dpaux_functions,
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.nfunctions = ARRAY_SIZE(tegra194_dpaux_functions),
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.powergate_id = TEGRA194_POWER_DOMAIN_DISP,
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},
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};
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static void tegra_dpaux_update(struct tegra_dpaux_pinctl *tdp_aux,
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u32 reg_offset, u32 mask, u32 val)
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{
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u32 rval;
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rval = __raw_readl(tdp_aux->regs + reg_offset);
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rval = (rval & ~mask) | (val & mask);
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__raw_writel(rval, tdp_aux->regs + reg_offset);
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}
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static int tegra_dpaux_pinctrl_set_mode(struct tegra_dpaux_pinctl *tdpaux_ctl,
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unsigned function)
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{
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int ret = 0;
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u32 mask;
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ret = clk_prepare_enable(tdpaux_ctl->dpaux_clk);
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if (ret < 0) {
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dev_err(tdpaux_ctl->dev, "clock enabled failed: %d\n", ret);
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return ret;
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}
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mask = I2C_SDA_INPUT | I2C_SCL_INPUT | MODE;
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if (function == TEGRA_DPAUX_MUX_DISPLAY)
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tegra_dpaux_update(tdpaux_ctl, DPAUX_HYBRID_PADCTL, mask, 0);
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else if (function == TEGRA_DPAUX_MUX_I2C)
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tegra_dpaux_update(tdpaux_ctl, DPAUX_HYBRID_PADCTL, mask, mask);
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tegra_dpaux_update(tdpaux_ctl, DPAUX_HYBRID_SPARE, 0x1, 0);
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clk_disable_unprepare(tdpaux_ctl->dpaux_clk);
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return ret;
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}
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static int tegra_dpaux_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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return padctl->npins;
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}
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static const char *tegra_dpaux_pinctrl_get_group_name(
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struct pinctrl_dev *pctldev, unsigned group)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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return padctl->pins[group].name;
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}
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static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
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.get_groups_count = tegra_dpaux_pinctrl_get_groups_count,
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.get_group_name = tegra_dpaux_pinctrl_get_group_name,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int tegra186_dpaux_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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return padctl->nfunctions;
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}
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static const char *tegra186_dpaux_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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return padctl->functions[function].name;
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}
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static int tegra186_dpaux_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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*num_groups = padctl->functions[function].ngroups;
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*groups = padctl->functions[function].groups;
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return 0;
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}
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static int tegra_dpaux_pinctrl_set_mux(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group)
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{
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struct tegra_dpaux_pinctl *padctl = pinctrl_dev_get_drvdata(pctldev);
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const struct tegra_dpaux_pingroup *g;
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int i;
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g = &padctl->groups[group];
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for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
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if (g->funcs[i] == function)
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break;
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}
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if (i == ARRAY_SIZE(g->funcs))
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return -EINVAL;
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return tegra_dpaux_pinctrl_set_mode(padctl, function);
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}
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static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
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.get_functions_count = tegra186_dpaux_get_functions_count,
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.get_function_name = tegra186_dpaux_get_function_name,
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.get_function_groups = tegra186_dpaux_get_function_groups,
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.set_mux = tegra_dpaux_pinctrl_set_mux,
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};
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static int tegra186_dpaux_pinctrl_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux_chip_data *cdata;
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struct tegra_dpaux_pinctl *tdpaux_ctl;
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struct reset_control *rst;
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int ret;
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tdpaux_ctl = devm_kzalloc(&pdev->dev, sizeof(*tdpaux_ctl), GFP_KERNEL);
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if (!tdpaux_ctl)
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return -ENOMEM;
|
||
|
|
|
||
|
|
tdpaux_ctl->dev = &pdev->dev;
|
||
|
|
cdata = (struct tegra_dpaux_chip_data *)
|
||
|
|
of_device_get_match_data(&pdev->dev);
|
||
|
|
|
||
|
|
tdpaux_ctl->pdev = pdev;
|
||
|
|
tdpaux_ctl->regs = devm_ioremap_resource(&pdev->dev,
|
||
|
|
platform_get_resource(pdev, IORESOURCE_MEM, 0));
|
||
|
|
if (!tdpaux_ctl->regs) {
|
||
|
|
dev_err(&pdev->dev, "Unable to map resource");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
tdpaux_ctl->pins = cdata->pins;
|
||
|
|
tdpaux_ctl->npins = cdata->npins;
|
||
|
|
tdpaux_ctl->functions = cdata->functions;
|
||
|
|
tdpaux_ctl->nfunctions = cdata->nfunctions;
|
||
|
|
tdpaux_ctl->groups = cdata->pin_group;
|
||
|
|
tdpaux_ctl->ngroups = cdata->npin_groups;
|
||
|
|
|
||
|
|
memset(&tdpaux_ctl->desc, 0, sizeof(tdpaux_ctl->desc));
|
||
|
|
tdpaux_ctl->desc.name = dev_name(&pdev->dev);
|
||
|
|
tdpaux_ctl->desc.pins = tdpaux_ctl->pins;
|
||
|
|
tdpaux_ctl->desc.npins = tdpaux_ctl->npins;
|
||
|
|
tdpaux_ctl->desc.pctlops = &tegra_dpaux_pinctrl_ops;
|
||
|
|
tdpaux_ctl->desc.pmxops = &tegra_dpaux_pinmux_ops;
|
||
|
|
tdpaux_ctl->desc.owner = THIS_MODULE;
|
||
|
|
tdpaux_ctl->powergate_id = cdata->powergate_id;
|
||
|
|
platform_set_drvdata(pdev, tdpaux_ctl);
|
||
|
|
|
||
|
|
ret = tegra_unpowergate_partition(tdpaux_ctl->powergate_id);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(tdpaux_ctl->dev, "unpowergate failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
tdpaux_ctl->dpaux_clk = devm_clk_get(&pdev->dev, NULL);
|
||
|
|
if (IS_ERR(tdpaux_ctl->dpaux_clk)) {
|
||
|
|
dev_err(&pdev->dev, "can not get clock\n");
|
||
|
|
return PTR_ERR(tdpaux_ctl->dpaux_clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
rst = devm_reset_control_get(&pdev->dev, NULL);
|
||
|
|
if (IS_ERR(rst)) {
|
||
|
|
dev_err(&pdev->dev, "can not get reset\n");
|
||
|
|
return PTR_ERR(rst);
|
||
|
|
}
|
||
|
|
|
||
|
|
reset_control_deassert(rst);
|
||
|
|
tdpaux_ctl->pinctrl = devm_pinctrl_register(&pdev->dev,
|
||
|
|
&tdpaux_ctl->desc, tdpaux_ctl);
|
||
|
|
if (IS_ERR(tdpaux_ctl->pinctrl)) {
|
||
|
|
ret = PTR_ERR(tdpaux_ctl->pinctrl);
|
||
|
|
dev_err(&pdev->dev, "Failed to register dpaux pinctrl: %d\n",
|
||
|
|
ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_dpaux_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct tegra_dpaux_pinctl *tdpaux_ctl = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
tegra_powergate_partition(tdpaux_ctl->powergate_id);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void tegra186_dpaux_save(struct tegra_dpaux_pinctl *dpaux_ctl)
|
||
|
|
{
|
||
|
|
dpaux_ctl->dpaux_context.val_padctl =
|
||
|
|
__raw_readl(dpaux_ctl->regs + DPAUX_HYBRID_PADCTL);
|
||
|
|
|
||
|
|
dpaux_ctl->dpaux_context.val_spare =
|
||
|
|
__raw_readl(dpaux_ctl->regs + DPAUX_HYBRID_SPARE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void tegra186_dpaux_restore(struct tegra_dpaux_pinctl *dpaux_ctl)
|
||
|
|
{
|
||
|
|
__raw_writel(dpaux_ctl->dpaux_context.val_padctl,
|
||
|
|
dpaux_ctl->regs + DPAUX_HYBRID_PADCTL);
|
||
|
|
__raw_writel(dpaux_ctl->dpaux_context.val_spare,
|
||
|
|
dpaux_ctl->regs + DPAUX_HYBRID_SPARE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra186_dpaux_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct tegra_dpaux_pinctl *dpaux_ctl = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(dpaux_ctl->dpaux_clk);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dpaux_ctl->dev, "clock enable failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
tegra186_dpaux_save(dpaux_ctl);
|
||
|
|
|
||
|
|
clk_disable_unprepare(dpaux_ctl->dpaux_clk);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra186_dpaux_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct tegra_dpaux_pinctl *dpaux_ctl = dev_get_drvdata(dev);
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(dpaux_ctl->dpaux_clk);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dpaux_ctl->dev, "clock enabled failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
tegra186_dpaux_restore(dpaux_ctl);
|
||
|
|
|
||
|
|
clk_disable_unprepare(dpaux_ctl->dpaux_clk);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dev_pm_ops tegra186_dpaux_pm_ops = {
|
||
|
|
.suspend = tegra186_dpaux_suspend,
|
||
|
|
.resume = tegra186_dpaux_resume,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct of_device_id tegra_dpaux_pinctl_of_match[] = {
|
||
|
|
{.compatible = "nvidia,tegra186-dpaux-padctl",
|
||
|
|
.data = &tegra186_dpaux_chip_data[0]},
|
||
|
|
{.compatible = "nvidia,tegra186-dpaux1-padctl",
|
||
|
|
.data = &tegra186_dpaux_chip_data[1]},
|
||
|
|
{.compatible = "nvidia,tegra194-dpaux-padctl",
|
||
|
|
.data = &tegra194_dpaux_chip_data[0]},
|
||
|
|
{.compatible = "nvidia,tegra194-dpaux1-padctl",
|
||
|
|
.data = &tegra194_dpaux_chip_data[1]},
|
||
|
|
{.compatible = "nvidia,tegra194-dpaux2-padctl",
|
||
|
|
.data = &tegra194_dpaux_chip_data[2]},
|
||
|
|
{.compatible = "nvidia,tegra194-dpaux3-padctl",
|
||
|
|
.data = &tegra194_dpaux_chip_data[3]},
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, tegra_dpaux_pinctl_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver tegra186_dpaux_pinctrl = {
|
||
|
|
.driver = {
|
||
|
|
.name = "tegra186-dpaux-pinctrl",
|
||
|
|
.of_match_table = tegra_dpaux_pinctl_of_match,
|
||
|
|
.pm = &tegra186_dpaux_pm_ops,
|
||
|
|
},
|
||
|
|
.probe = tegra186_dpaux_pinctrl_probe,
|
||
|
|
.remove = tegra_dpaux_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
module_platform_driver(tegra186_dpaux_pinctrl);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("NVIDIA Tegra dpaux pinctrl driver");
|
||
|
|
MODULE_AUTHOR("Suresh Mangipudi <smangipudi@nvidia.com>");
|
||
|
|
MODULE_ALIAS("platform:tegra186-dpaux");
|
||
|
|
MODULE_LICENSE("GPL v2");
|