191 lines
4.8 KiB
C
191 lines
4.8 KiB
C
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/**
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <linux/platform/tegra/isomgr.h>
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#include <linux/debugfs.h>
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#include <linux/io.h>
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#include "../../../../arch/arm/mach-tegra/iomap.h"
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static u32 bwmgr_t210_iso_bw_table[] = { /* MHz */
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5, 10, 20, 30, 40, 60, 80, 100, 120, 140,
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160, 180, 200, 250, 300, 350, 360, 370, 380, 400,
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450, 500, 550, 600, 650, 700
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};
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/* value of 1 indicates the range over max ISO Bw allowed for the DRAM type */
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static u32 bwmgr_t210_lpddr4_iso_eff[] = {
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56, 56, 56, 56, 56, 56, 56, 56, 56, 56,
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56, 56, 56, 56, 56, 56, 56, 56, 56, 56,
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56, 56, 56, 56, 49, 45
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};
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static u32 bwmgr_t210_lpddr3_iso_eff[] = {
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64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
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64, 64, 64, 63, 60, 54, 45, 1, 1, 1,
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1, 1, 1, 1, 1, 1
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};
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static u32 bwmgr_t210_ddr3_iso_eff[] = {
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65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
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65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
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65, 65, 65, 65, 65, 1
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};
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#define EMC_FBIO_CFG5_0 0x104
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#define DRAM_MASK 0x3
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#define DRAM_DDR3 0
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#define DRAM_LPDDR4 1
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#define DRAM_LPDDR3 2 /* On T210 this value is LPDDR3 */
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static int get_iso_bw_table_idx(unsigned long iso_bw)
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{
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int i = ARRAY_SIZE(bwmgr_t210_iso_bw_table) - 1;
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/* Input is in Hz, iso_bw table's unit is MHz */
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iso_bw /= 1000000;
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while (i > 0 && bwmgr_t210_iso_bw_table[i] > iso_bw)
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i--;
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return i;
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}
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static unsigned long freq_to_bw(unsigned long freq)
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{
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if (bwmgr_dram_type == DRAM_TYPE_LPDDR4_4CH_ECC ||
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bwmgr_dram_type == DRAM_TYPE_LPDDR4_4CH ||
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bwmgr_dram_type == DRAM_TYPE_LPDDR3_2CH ||
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bwmgr_dram_type == DRAM_TYPE_DDR3_2CH)
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return freq * 32;
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return freq * 16;
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}
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static unsigned long bw_to_freq(unsigned long bw)
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{
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if (bwmgr_dram_type == DRAM_TYPE_LPDDR4_4CH_ECC ||
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bwmgr_dram_type == DRAM_TYPE_LPDDR4_4CH ||
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bwmgr_dram_type == DRAM_TYPE_LPDDR3_2CH ||
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bwmgr_dram_type == DRAM_TYPE_DDR3_2CH)
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return (bw + 32 - 1) / 32;
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return (bw + 16 - 1) / 16;
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}
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static u32 dvfs_latency(u32 ufreq)
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{
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return 4;
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}
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static unsigned long t21x_bwmgr_apply_efficiency(
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unsigned long total_bw, unsigned long iso_bw,
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unsigned long max_rate, u64 usage_flags,
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unsigned long *iso_bw_min, unsigned long iso_bw_nvdis,
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unsigned long iso_bw_vi)
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{
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u8 efficiency = bwmgr_dram_efficiency;
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if (total_bw && efficiency && (efficiency < 100)) {
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total_bw = total_bw / efficiency;
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total_bw = (total_bw < max_rate / 100) ?
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(total_bw * 100) : max_rate;
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}
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efficiency = bwmgr_dram_iso_eff_table[get_iso_bw_table_idx(iso_bw)];
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WARN_ON(efficiency == 1);
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if (iso_bw && efficiency && (efficiency < 100)) {
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iso_bw /= efficiency;
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iso_bw = (iso_bw < max_rate / 100) ?
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(iso_bw * 100) : max_rate;
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}
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if (iso_bw_min)
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*iso_bw_min = iso_bw;
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return max(total_bw, iso_bw);
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}
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static struct bwmgr_ops bwmgr_ops_t21x = {
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.freq_to_bw = freq_to_bw,
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.bw_to_freq = bw_to_freq,
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.dvfs_latency = dvfs_latency,
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.bwmgr_apply_efficiency = t21x_bwmgr_apply_efficiency,
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};
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struct bwmgr_ops *bwmgr_eff_init_t21x(void)
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{
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int i;
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u32 dram;
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void __iomem *emc_base;
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emc_base = ioremap(TEGRA_T210_EMC_BASE, TEGRA_T210_EMC_SIZE);
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dram = readl(emc_base + EMC_FBIO_CFG5_0) & DRAM_MASK;
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iounmap(emc_base);
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switch (dram) {
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case DRAM_LPDDR4:
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bwmgr_dram_type = DRAM_TYPE_LPDDR4_2CH;
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bwmgr_dram_iso_eff_table = bwmgr_t210_lpddr4_iso_eff;
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bwmgr_dram_efficiency = 70;
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emc_to_dram_freq_factor = 2;
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/* valid ddr configuration */
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bwmgr_dram_config_supported = 1;
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break;
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case DRAM_LPDDR3:
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bwmgr_dram_type = DRAM_TYPE_LPDDR3_2CH;
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bwmgr_dram_efficiency = 80;
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bwmgr_dram_iso_eff_table = bwmgr_t210_lpddr3_iso_eff;
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emc_to_dram_freq_factor = 1;
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/* valid ddr configuration */
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bwmgr_dram_config_supported = 1;
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break;
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case DRAM_DDR3:
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bwmgr_dram_type = DRAM_TYPE_DDR3_2CH;
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bwmgr_dram_efficiency = 80;
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bwmgr_dram_iso_eff_table = bwmgr_t210_ddr3_iso_eff;
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emc_to_dram_freq_factor = 1;
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/* valid ddr configuration */
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bwmgr_dram_config_supported = 1;
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break;
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default:
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pr_err("bwmgr: ddr config not supported\n");
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WARN_ON(true);
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}
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bwmgr_dram_num_channels = 2;
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if (bwmgr_dram_config_supported) {
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for (i = ARRAY_SIZE(bwmgr_t210_iso_bw_table) - 1; i >= 0; i--) {
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if (bwmgr_dram_iso_eff_table[i] > 1) {
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bwmgr_iso_bw_percentage =
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bwmgr_dram_iso_eff_table[i];
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break;
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}
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}
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}
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return &bwmgr_ops_t21x;
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}
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