495 lines
13 KiB
C
495 lines
13 KiB
C
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/*
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* Tegra 12x SoC-specific mcerr code.
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*
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* Copyright (c) 2014-2017, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define pr_fmt(fmt) "mc-err: " fmt
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#include <linux/of.h>
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#include <linux/moduleparam.h>
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#include <linux/version.h>
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#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 13, 0)
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#include <linux/sched/clock.h>
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#endif
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#include <linux/platform/tegra/mc-regs-t21x.h>
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#include <linux/platform/tegra/mcerr.h>
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#include <dt-bindings/memory/tegra-swgroup.h>
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/*** Auto generated by `mcp.pl'. Do not modify! ***/
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static struct mc_client mc_clients[] = {
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client("ptc", "csr_ptcr", INVALID),
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client("dc", "csr_display0a", DC),
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client("dcb", "csr_display0ab", DCB),
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client("dc", "csr_display0b", DC),
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client("dcb", "csr_display0bb", DCB),
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client("dc", "csr_display0c", DC),
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client("dcb", "csr_display0cb", DCB),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("afi", "csr_afir", AFI),
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client("avpc", "csr_avpcarm7r", AVPC),
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client("dc", "csr_displayhc", DC),
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client("dcb", "csr_displayhcb", DCB),
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dummy_client,
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dummy_client,
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dummy_client,
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client("hda", "csr_hdar", HDA),
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client("hc", "csr_host1xdmar", HC),
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client("hc", "csr_host1xr", HC),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvenc", "csr_nvencsrd", NVENC),
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client("ppcs", "csr_ppcsahbdmar", PPCS),
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client("ppcs", "csr_ppcsahbslvr", PPCS),
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client("sata", "csr_satar", SATA),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("mpcore", "csr_mpcorer", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvenc", "csw_nvencswr", NVENC),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("afi", "csw_afiw", AFI),
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client("avpc", "csw_avpcarm7w", AVPC),
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dummy_client,
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dummy_client,
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client("hda", "csw_hdaw", HDA),
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client("hc", "csw_host1xw", HC),
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dummy_client,
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dummy_client,
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client("mpcore", "csw_mpcorew", INVALID),
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dummy_client,
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client("ppcs", "csw_ppcsahbdmaw", PPCS),
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client("ppcs", "csw_ppcsahbslvw", PPCS),
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client("sata", "csw_sataw", SATA),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("isp2", "csr_ispra", ISP2),
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dummy_client,
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client("isp2", "csw_ispwa", ISP2),
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client("isp2", "csw_ispwb", ISP2),
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dummy_client,
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dummy_client,
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client("xusb_host", "csr_xusb_hostr", XUSB_HOST),
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client("xusb_host", "csw_xusb_hostw", XUSB_HOST),
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client("xusb_dev", "csr_xusb_devr", XUSB_DEV),
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client("xusb_dev", "csw_xusb_devw", XUSB_DEV),
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client("isp2b/se2", "csr_isprab/csr_se2srd", ISP2B), /* isp2b is replaced with se2 on T210b01 */
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dummy_client,
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client("isp2b/se2", "csw_ispw/csw_se2swr", ISP2B),
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client("isp2b/se2", "csw_ispwbb/unused", ISP2B),
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dummy_client,
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dummy_client,
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client("tsec", "csr_tsecsrd", TSEC),
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client("tsec", "csw_tsecswr", TSEC),
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client("a9avp", "csr_a9avpscr", A9AVP),
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client("a9avp", "csw_a9avpscw", A9AVP),
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client("gpu", "csr_gpusrd", GPU),
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client("gpu", "csw_gpuswr", GPU),
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client("dc", "csr_displayt", DC),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("sdmmc1a", "csr_sdmmcra", SDMMC1A),
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client("sdmmc2a", "csr_sdmmcraa", SDMMC2A),
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client("sdmmc3a", "csr_sdmmcr", SDMMC3A),
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client("sdmmc4a", "csr_sdmmcrab", SDMMC4A),
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client("sdmmc1a", "csw_sdmmcwa", SDMMC1A),
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client("sdmmc2a", "csw_sdmmcwaa", SDMMC2A),
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client("sdmmc3a", "csw_sdmmcw", SDMMC3A),
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client("sdmmc4a", "csw_sdmmcwab", SDMMC4A),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("vic", "csr_vicsrd", VIC),
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client("vic", "csw_vicswr", VIC),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("vi", "csw_viw", VI),
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client("dc", "csr_displayd", DC),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvdec", "csr_nvdecsrd", NVDEC),
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client("nvdec", "csw_nvdecswr", NVDEC),
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client("ape", "csr_aper", INVALID),
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client("ape", "csw_apew", INVALID),
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dummy_client,
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dummy_client,
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client("nvjpg", "csr_nvjpgsrd", NVJPG),
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client("nvjpg", "csw_nvjpgswr", NVJPG),
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client("se", "csr_sesrd", SE),
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client("se", "csw_seswr", SE),
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client("axiap", "csr_axiapr", INVALID),
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client("axiap", "csw_axiapw", INVALID),
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client("etr", "csr_etrr", INVALID),
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client("etr", "csw_etrw", INVALID),
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client("tsecb", "csr_tsecsrdb", TSECB),
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client("tsecb", "csw_tsecswrb", TSECB),
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client("gpu", "csr_gpusrd2", GPU),
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client("gpu", "csw_gpuswr2", GPU),
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};
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static int mc_client_last = ARRAY_SIZE(mc_clients) - 1;
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/*** Done. ***/
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static const char *t210_intr_info[] = {
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NULL, /* Bit 0 */
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NULL,
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NULL,
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NULL,
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NULL, /* Bit 4 */
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NULL,
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"decerr-emem",
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NULL,
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"secerr", /* Bit 8 */
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"arb-emem",
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"smmu-err",
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"apb_err",
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"decerr-vpr", /* Bit 12 */
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"decerr-sec",
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NULL,
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NULL,
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"decerr-mts", /* Bit 16 */
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"decerr-gsc",
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NULL,
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NULL,
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NULL, /* Bit 20 */
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NULL,
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"decerr-untranslated", /* specific to t210b01 */
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NULL,
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NULL, /* Bit 24 */
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NULL,
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NULL,
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NULL,
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NULL, /* Bit 28 */
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NULL,
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NULL,
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NULL,
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};
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/*
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* Some platforms report SMMU errors via the SMMU driver.
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*/
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static const char *const smmu_page_attrib[] = {
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"nr-nw-s",
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"nr-nw-ns",
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"nr-wr-s",
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"nr-wr-ns",
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"rd-nw-s",
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"rd-nw-ns",
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"rd-wr-s",
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"rd-wr-ns"
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};
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#define MC_INT_DECERR_UNTRANSLATED_VIOLATION (1<<22)
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#define MC_ERR_SMMU_MASK (0x7 << 25)
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#define MC_ERR_SMMU_BITS(err) (((err) & MC_ERR_SMMU_MASK) >> 25)
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#define MC_INT_INVALID_SMMU_PAGE (1<<10)
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#define MC_INT_INVALID_APB_ASID_UPDATE (1<<11)
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/*
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* Table of known errors and their interrupt signatures.
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*/
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static const struct mc_error mc_errors[] = {
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MC_ERR(MC_INT_DECERR_EMEM,
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"EMEM address decode error",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_DECERR_VPR,
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"MC request violates VPR requirements",
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E_VPR, MC_ERR_VPR_STATUS, MC_ERR_VPR_ADR),
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MC_ERR(MC_INT_SECURITY_VIOLATION,
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"non secure access to secure region",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION,
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"non secure access to secure region",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_SECERR_SEC,
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"MC request violated SEC carveout requirements",
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0, MC_ERR_SEC_STATUS, MC_ERR_SEC_ADR),
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/*
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* SMMU related faults.
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*/
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MC_ERR(MC_INT_INVALID_SMMU_PAGE,
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"SMMU address translation fault",
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E_SMMU, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_INVALID_SMMU_PAGE | MC_INT_DECERR_EMEM,
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"EMEM decode error on PDE or PTE entry",
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E_SMMU, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_INVALID_SMMU_PAGE | MC_INT_SECERR_SEC,
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"secure SMMU address translation fault",
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E_SMMU, MC_ERR_SEC_STATUS, MC_ERR_SEC_ADR),
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MC_ERR(MC_INT_INVALID_SMMU_PAGE | MC_INT_DECERR_VPR,
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"VPR SMMU address translation fault",
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E_VPR | E_SMMU, MC_ERR_VPR_STATUS, MC_ERR_VPR_ADR),
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MC_ERR(MC_INT_INVALID_SMMU_PAGE | MC_INT_DECERR_VPR |
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MC_INT_DECERR_EMEM,
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"EMEM decode error on PDE or PTE entry on VPR context",
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E_VPR | E_SMMU, MC_ERR_VPR_STATUS, MC_ERR_VPR_ADR),
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/*
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* Generalized carveouts.
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*/
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MC_ERR(MC_INT_DECERR_GENERALIZED_CARVEOUT,
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"GSC access violation", 0,
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MC_ERR_GENERALIZED_CARVEOUT_STATUS,
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MC_ERR_GENERALIZED_CARVEOUT_ADR),
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MC_ERR(MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_EMEM,
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"EMEM GSC access violation", 0,
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MC_ERR_GENERALIZED_CARVEOUT_STATUS,
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MC_ERR_GENERALIZED_CARVEOUT_ADR),
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MC_ERR(MC_INT_DECERR_UNTRANSLATED_VIOLATION,
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"Untranslated memory access violation",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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/*
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* Miscellaneous errors.
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*/
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MC_ERR(MC_INT_INVALID_APB_ASID_UPDATE,
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"invalid APB ASID update", 0,
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MC_ERR_STATUS, MC_ERR_ADR),
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/* NULL terminate. */
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MC_ERR(0, NULL, 0, 0, 0),
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};
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static int arb_intr_mma_set(const char *arg, const struct kernel_param *kp);
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static int arb_intr_mma_get(char *buff, const struct kernel_param *kp);
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static struct arb_emem_intr_info arb_intr_info = {
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.lock = __SPIN_LOCK_UNLOCKED(arb_intr_info.lock),
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};
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static int arb_intr_count;
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static struct kernel_param_ops arb_intr_mma_ops = {
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.get = arb_intr_mma_get,
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.set = arb_intr_mma_set,
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};
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module_param_cb(arb_intr_mma_in_ms, &arb_intr_mma_ops,
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&arb_intr_info.arb_intr_mma, S_IRUGO | S_IWUSR);
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module_param(arb_intr_count, int, S_IRUGO | S_IWUSR);
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static int arb_intr_mma_set(const char *arg, const struct kernel_param *kp)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&arb_intr_info.lock, flags);
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ret = param_set_int(arg, kp);
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spin_unlock_irqrestore(&arb_intr_info.lock, flags);
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return ret;
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}
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static int arb_intr_mma_get(char *buff, const struct kernel_param *kp)
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{
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return param_get_int(buff, kp);
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}
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static const struct mc_error *mcerr_default_info(u32 intr)
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{
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const struct mc_error *err;
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for (err = mc_errors; err->sig && err->msg; err++) {
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if (intr != err->sig)
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||
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|
continue;
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
void __weak smmu_dump_pagetable(int swgid, dma_addr_t addr)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This will print at least 8 hex digits for address. If the address is bigger
|
||
|
|
* then more digits will be printed but the full 16 hex digits for a 64 bit
|
||
|
|
* address will not get printed by the current code.
|
||
|
|
*/
|
||
|
|
static void mcerr_default_print(const struct mc_error *err,
|
||
|
|
const struct mc_client *client,
|
||
|
|
u32 status, phys_addr_t addr,
|
||
|
|
int secure, int rw, const char *smmu_info)
|
||
|
|
{
|
||
|
|
if (smmu_info)
|
||
|
|
smmu_dump_pagetable(client->swgid, addr);
|
||
|
|
|
||
|
|
if (err->flags & E_VPR)
|
||
|
|
mcerr_pr("vpr base=%x:%x, size=%x, ctrl=%x, override:(%x, %x, %x, %x)\n",
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_BOM_ADR_HI),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_BOM),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_SIZE_MB),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_REG_CTRL),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_VPR_OVERRIDE),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_VPR_OVERRIDE1),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_GPU_OVERRIDE_0),
|
||
|
|
mc_readl(MC_VIDEO_PROTECT_GPU_OVERRIDE_1));
|
||
|
|
|
||
|
|
mcerr_pr("(%d) %s: %s\n", client->swgid, client->name, err->msg);
|
||
|
|
mcerr_pr(" status = 0x%08x; addr = 0x%08llx\n", status,
|
||
|
|
(long long unsigned int)addr);
|
||
|
|
mcerr_pr(" secure: %s, access-type: %s, SMMU fault: %s\n",
|
||
|
|
secure ? "yes" : "no", rw ? "write" : "read",
|
||
|
|
smmu_info ? smmu_info : "none");
|
||
|
|
}
|
||
|
|
|
||
|
|
static void arb_intr(void)
|
||
|
|
{
|
||
|
|
u64 time;
|
||
|
|
u32 time_diff_ms;
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&arb_intr_info.lock, flags);
|
||
|
|
arb_intr_count++;
|
||
|
|
time = sched_clock();
|
||
|
|
time_diff_ms = (time - arb_intr_info.time) >> 20;
|
||
|
|
arb_intr_info.time = time;
|
||
|
|
arb_intr_info.arb_intr_mma =
|
||
|
|
((MMA_HISTORY_SAMPLES - 1) * time_diff_ms +
|
||
|
|
arb_intr_info.arb_intr_mma) / MMA_HISTORY_SAMPLES;
|
||
|
|
spin_unlock_irqrestore(&arb_intr_info.lock, flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void clear_interrupt(unsigned int irq)
|
||
|
|
{
|
||
|
|
mc_writel(0x00033F40, MC_INTSTATUS);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mcerr_info_update(struct mc_client *c, u32 stat)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < (sizeof(stat) * 8); i++) {
|
||
|
|
if (stat & (1 << i))
|
||
|
|
c->intr_counts[i]++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void log_mcerr_fault(unsigned int irq)
|
||
|
|
{
|
||
|
|
struct mc_client *client;
|
||
|
|
const struct mc_error *fault;
|
||
|
|
const char *smmu_info;
|
||
|
|
phys_addr_t addr;
|
||
|
|
u32 status, write, secure, client_id;
|
||
|
|
int src_chan = MC_BROADCAST_CHANNEL;
|
||
|
|
u32 intstatus = mc_int_mask &
|
||
|
|
__mc_readl(src_chan, MC_INTSTATUS);
|
||
|
|
|
||
|
|
|
||
|
|
if (intstatus & MC_INT_ARBITRATION_EMEM) {
|
||
|
|
arb_intr();
|
||
|
|
if (intstatus == MC_INT_ARBITRATION_EMEM)
|
||
|
|
goto end;
|
||
|
|
intstatus &= ~MC_INT_ARBITRATION_EMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
fault = mcerr_default_info(intstatus & mc_int_mask);
|
||
|
|
if (WARN(!fault, "Unknown error! intr sig: 0x%08x\n",
|
||
|
|
intstatus & mc_int_mask))
|
||
|
|
goto end;
|
||
|
|
|
||
|
|
if (fault->flags & E_NO_STATUS) {
|
||
|
|
mcerr_pr("MC fault - no status: %s\n", fault->msg);
|
||
|
|
goto end;
|
||
|
|
}
|
||
|
|
|
||
|
|
status = __mc_readl(src_chan, fault->stat_reg);
|
||
|
|
addr = __mc_readl(src_chan, fault->addr_reg);
|
||
|
|
|
||
|
|
if (fault->flags & E_TWO_STATUS) {
|
||
|
|
mcerr_pr("MC fault - %s\n", fault->msg);
|
||
|
|
mcerr_pr("status: 0x%08x status2: 0x%08llx\n",
|
||
|
|
status, addr);
|
||
|
|
goto end;
|
||
|
|
}
|
||
|
|
|
||
|
|
secure = !!(status & MC_ERR_STATUS_SECURE);
|
||
|
|
write = !!(status & MC_ERR_STATUS_WRITE);
|
||
|
|
client_id = status & 0xff;
|
||
|
|
client = &mc_clients[client_id <= mc_client_last
|
||
|
|
? client_id : mc_client_last];
|
||
|
|
|
||
|
|
mcerr_info_update(client, intstatus & mc_int_mask);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* LPAE: make sure we get the extra 2 physical address bits available
|
||
|
|
* and pass them down to the printing function.
|
||
|
|
*/
|
||
|
|
addr |= (((phys_addr_t)(status & MC_ERR_STATUS_ADR_HI)) << 12);
|
||
|
|
|
||
|
|
if (fault->flags & E_SMMU)
|
||
|
|
smmu_info = smmu_page_attrib[MC_ERR_SMMU_BITS(status)];
|
||
|
|
else
|
||
|
|
smmu_info = NULL;
|
||
|
|
|
||
|
|
mcerr_default_print(fault, client, status, addr, secure, write,
|
||
|
|
smmu_info);
|
||
|
|
end:
|
||
|
|
mc_writel(intstatus, MC_INTSTATUS);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct mcerr_ops mcerr_ops = {
|
||
|
|
.clear_interrupt = clear_interrupt,
|
||
|
|
.log_mcerr_fault = log_mcerr_fault,
|
||
|
|
.nr_clients = ARRAY_SIZE(mc_clients),
|
||
|
|
.intr_descriptions = t210_intr_info,
|
||
|
|
.mc_clients = mc_clients,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct mcerr_ops *t21x_mcerr_of_setup(struct device_node *np)
|
||
|
|
{
|
||
|
|
pr_info("mcerr ops are set to t21x\n");
|
||
|
|
return &mcerr_ops;
|
||
|
|
}
|
||
|
|
|
||
|
|
MCERR_OF_DECLARE(mcerr_of, "nvidia,tegra-mc", t21x_mcerr_of_setup);
|