540 lines
8.7 KiB
C
540 lines
8.7 KiB
C
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/*
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* Tegra186 MC StreamID configuration
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "%s(): " fmt, __func__
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform/tegra/tegra-mc-sid.h>
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#include <dt-bindings/memory/tegra-swgroup.h>
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enum override_id {
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PTCR,
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AFIR,
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HDAR,
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HOST1XDMAR,
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NVENCSRD,
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SATAR,
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MPCORER,
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NVENCSWR,
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AFIW,
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HDAW,
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MPCOREW,
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SATAW,
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ISPRA,
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ISPWA,
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ISPWB,
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XUSB_HOSTR,
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XUSB_HOSTW,
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XUSB_DEVR,
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XUSB_DEVW,
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TSECSRD,
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TSECSWR,
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GPUSRD,
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GPUSWR,
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SDMMCRA,
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SDMMCRAA,
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SDMMCR,
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SDMMCRAB,
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SDMMCWA,
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SDMMCWAA,
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SDMMCW,
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SDMMCWAB,
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VICSRD,
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VICSWR,
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VIW,
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NVDECSRD,
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NVDECSWR,
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APER,
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APEW,
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NVJPGSRD,
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NVJPGSWR,
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SESRD,
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SESWR,
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ETRR,
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ETRW,
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TSECSRDB,
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TSECSWRB,
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GPUSRD2,
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GPUSWR2,
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AXISR,
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AXISW,
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EQOSR,
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EQOSW,
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UFSHCR,
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UFSHCW,
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NVDISPLAYR,
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BPMPR,
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BPMPW,
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BPMPDMAR,
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BPMPDMAW,
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AONR,
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AONW,
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AONDMAR,
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AONDMAW,
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SCER,
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SCEW,
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SCEDMAR,
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SCEDMAW,
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APEDMAR,
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APEDMAW,
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NVDISPLAYR1,
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VICSRD1,
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NVDECSRD1,
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MAX_OID,
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};
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static struct sid_override_reg sid_override_reg[] = {
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DEFREG(PTCR, 0x000),
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DEFREG(AFIR, 0x070),
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DEFREG(HDAR, 0x0a8),
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DEFREG(HOST1XDMAR, 0x0b0),
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DEFREG(NVENCSRD, 0x0e0),
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DEFREG(SATAR, 0x0f8),
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DEFREG(MPCORER, 0x138),
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DEFREG(NVENCSWR, 0x158),
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DEFREG(AFIW, 0x188),
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DEFREG(HDAW, 0x1a8),
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DEFREG(MPCOREW, 0x1c8),
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DEFREG(SATAW, 0x1e8),
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DEFREG(ISPRA, 0x220),
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DEFREG(ISPWA, 0x230),
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DEFREG(ISPWB, 0x238),
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DEFREG(XUSB_HOSTR, 0x250),
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DEFREG(XUSB_HOSTW, 0x258),
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DEFREG(XUSB_DEVR, 0x260),
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DEFREG(XUSB_DEVW, 0x268),
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DEFREG(TSECSRD, 0x2a0),
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DEFREG(TSECSWR, 0x2a8),
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DEFREG(GPUSRD, 0x2c0),
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DEFREG(GPUSWR, 0x2c8),
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DEFREG(SDMMCRA, 0x300),
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DEFREG(SDMMCRAA, 0x308),
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DEFREG(SDMMCR, 0x310),
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DEFREG(SDMMCRAB, 0x318),
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DEFREG(SDMMCWA, 0x320),
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DEFREG(SDMMCWAA, 0x328),
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DEFREG(SDMMCW, 0x330),
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DEFREG(SDMMCWAB, 0x338),
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DEFREG(VICSRD, 0x360),
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DEFREG(VICSWR, 0x368),
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DEFREG(VIW, 0x390),
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DEFREG(NVDECSRD, 0x3c0),
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DEFREG(NVDECSWR, 0x3c8),
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DEFREG(APER, 0x3d0),
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DEFREG(APEW, 0x3d8),
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DEFREG(NVJPGSRD, 0x3f0),
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DEFREG(NVJPGSWR, 0x3f8),
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DEFREG(SESRD, 0x400),
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DEFREG(SESWR, 0x408),
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DEFREG(ETRR, 0x420),
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DEFREG(ETRW, 0x428),
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DEFREG(TSECSRDB, 0x430),
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DEFREG(TSECSWRB, 0x438),
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DEFREG(GPUSRD2, 0x440),
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DEFREG(GPUSWR2, 0x448),
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DEFREG(AXISR, 0x460),
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DEFREG(AXISW, 0x468),
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DEFREG(EQOSR, 0x470),
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DEFREG(EQOSW, 0x478),
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DEFREG(UFSHCR, 0x480),
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DEFREG(UFSHCW, 0x488),
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DEFREG(NVDISPLAYR, 0x490),
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DEFREG(BPMPR, 0x498),
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DEFREG(BPMPW, 0x4a0),
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DEFREG(BPMPDMAR, 0x4a8),
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DEFREG(BPMPDMAW, 0x4b0),
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DEFREG(AONR, 0x4b8),
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DEFREG(AONW, 0x4c0),
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DEFREG(AONDMAR, 0x4c8),
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DEFREG(AONDMAW, 0x4d0),
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DEFREG(SCER, 0x4d8),
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DEFREG(SCEW, 0x4e0),
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DEFREG(SCEDMAR, 0x4e8),
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DEFREG(SCEDMAW, 0x4f0),
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DEFREG(APEDMAR, 0x4f8),
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DEFREG(APEDMAW, 0x500),
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DEFREG(NVDISPLAYR1, 0x508),
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DEFREG(VICSRD1, 0x510),
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DEFREG(NVDECSRD1, 0x518),
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};
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static struct sid_to_oids sid_to_oids[] = {
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{
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.sid = TEGRA_SID_AFI,
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.noids = 2,
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.oid = {
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AFIR,
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AFIW,
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},
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.ord = OVERRIDE,
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.name = "AFI",
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},
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{
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.sid = TEGRA_SID_HDA,
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.noids = 2,
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.oid = {
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HDAR,
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HDAW,
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},
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.ord = OVERRIDE,
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.name = "HDA",
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},
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{
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.sid = TEGRA_SID_SATA2,
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.noids = 2,
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.oid = {
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SATAR,
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SATAW,
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},
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.ord = OVERRIDE,
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.name = "SATA2",
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},
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{
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.sid = TEGRA_SID_XUSB_HOST,
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.noids = 2,
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.oid = {
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XUSB_HOSTR,
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XUSB_HOSTW,
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},
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.ord = OVERRIDE,
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.name = "XUSB_HOST",
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},
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{
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.sid = TEGRA_SID_XUSB_DEV,
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.noids = 2,
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.oid = {
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XUSB_DEVR,
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XUSB_DEVW,
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},
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.ord = OVERRIDE,
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.name = "XUSB_DEV",
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},
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{
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.sid = TEGRA_SID_TSEC,
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.noids = 2,
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.oid = {
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TSECSRD,
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TSECSWR,
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},
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.ord = SIM_OVERRIDE,
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.name = "TSEC",
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},
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{
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.sid = TEGRA_SID_GPUB,
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.noids = 4,
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.oid = {
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GPUSRD,
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GPUSWR,
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GPUSRD2,
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GPUSWR2,
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},
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.ord = NO_OVERRIDE,
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.name = "GPU",
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},
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{
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.sid = TEGRA_SID_SDMMC1A,
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.noids = 2,
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.oid = {
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SDMMCRA,
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SDMMCWA,
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},
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.ord = OVERRIDE,
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.name = "SDMMC1A",
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},
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{
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.sid = TEGRA_SID_SDMMC2A,
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.noids = 2,
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.oid = {
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SDMMCRAA,
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SDMMCWAA,
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},
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.ord = OVERRIDE,
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.name = "SDMMC2A",
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},
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{
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.sid = TEGRA_SID_SDMMC3A,
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.noids = 2,
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.oid = {
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SDMMCR,
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SDMMCW,
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},
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.ord = OVERRIDE,
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.name = "SDMMC3A",
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},
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{
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.sid = TEGRA_SID_SDMMC4A,
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.noids = 2,
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.oid = {
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SDMMCRAB,
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SDMMCWAB,
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},
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.ord = OVERRIDE,
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.name = "SDMMC4A",
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},
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{
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.sid = TEGRA_SID_APE,
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.noids = 4,
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.oid = {
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APER,
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APEW,
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APEDMAR,
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APEDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "APE",
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},
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{
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.sid = TEGRA_SID_SE,
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.noids = 2,
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.oid = {
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SESRD,
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SESWR,
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},
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.ord = NO_OVERRIDE,
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.name = "SE",
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},
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{
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.sid = TEGRA_SID_ETR,
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.noids = 2,
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.oid = {
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ETRR,
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ETRW,
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},
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.ord = OVERRIDE,
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.name = "ETR",
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},
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{
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.sid = TEGRA_SID_TSECB,
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.noids = 2,
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.oid = {
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TSECSRDB,
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TSECSWRB,
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},
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.ord = SIM_OVERRIDE,
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.name = "TSECB",
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},
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{
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.sid = TEGRA_SID_GPCDMA_0, /* AXIS */
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.noids = 2,
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.oid = {
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AXISR,
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AXISW,
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},
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.ord = NO_OVERRIDE,
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.name = "GPCDMA",
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},
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{
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.sid = TEGRA_SID_EQOS,
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.noids = 2,
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.oid = {
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EQOSR,
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EQOSW,
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},
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.ord = OVERRIDE,
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.name = "EQOS",
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},
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{
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.sid = TEGRA_SID_UFSHC,
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.noids = 2,
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.oid = {
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UFSHCR,
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UFSHCW,
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},
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.ord = OVERRIDE,
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.name = "UFSHC",
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},
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{
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.sid = TEGRA_SID_NVDISPLAY,
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.noids = 2,
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.oid = {
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NVDISPLAYR,
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NVDISPLAYR1,
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},
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.ord = OVERRIDE,
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.name = "NVDISPLAY",
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},
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{
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.sid = TEGRA_SID_BPMP,
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.noids = 4,
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.oid = {
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BPMPR,
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BPMPW,
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BPMPDMAR,
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BPMPDMAW,
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},
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.ord = NO_OVERRIDE,
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.name = "BPMP",
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},
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{
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.sid = TEGRA_SID_AON,
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.noids = 4,
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.oid = {
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AONR,
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AONW,
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AONDMAR,
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AONDMAW,
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},
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.ord = NO_OVERRIDE,
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||
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|
.name = "AON",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_SCE,
|
||
|
|
.noids = 4,
|
||
|
|
.oid = {
|
||
|
|
SCER,
|
||
|
|
SCEW,
|
||
|
|
SCEDMAR,
|
||
|
|
SCEDMAW,
|
||
|
|
},
|
||
|
|
.ord = NO_OVERRIDE,
|
||
|
|
.name = "SCE",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_HC,
|
||
|
|
.noids = 1,
|
||
|
|
.oid = {
|
||
|
|
HOST1XDMAR,
|
||
|
|
},
|
||
|
|
.ord = SIM_OVERRIDE,
|
||
|
|
.name = "HC",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_VIC,
|
||
|
|
.noids = 3,
|
||
|
|
.oid = {
|
||
|
|
VICSRD1,
|
||
|
|
VICSRD,
|
||
|
|
VICSWR,
|
||
|
|
},
|
||
|
|
.ord = SIM_OVERRIDE,
|
||
|
|
.name = "VIC",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_VI,
|
||
|
|
.noids = 1,
|
||
|
|
.oid = {
|
||
|
|
VIW,
|
||
|
|
},
|
||
|
|
.ord = OVERRIDE,
|
||
|
|
.name = "VI",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_ISP,
|
||
|
|
.noids = 3,
|
||
|
|
.oid = {
|
||
|
|
ISPRA,
|
||
|
|
ISPWA,
|
||
|
|
ISPWB,
|
||
|
|
},
|
||
|
|
.ord = OVERRIDE,
|
||
|
|
.name = "ISP",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_NVDEC,
|
||
|
|
.noids = 3,
|
||
|
|
.oid = {
|
||
|
|
NVDECSRD1,
|
||
|
|
NVDECSRD,
|
||
|
|
NVDECSWR,
|
||
|
|
},
|
||
|
|
.ord = SIM_OVERRIDE,
|
||
|
|
.name = "NVDEC",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_NVENC,
|
||
|
|
.noids = 2,
|
||
|
|
.oid = {
|
||
|
|
NVENCSRD,
|
||
|
|
NVENCSWR,
|
||
|
|
},
|
||
|
|
.ord = SIM_OVERRIDE,
|
||
|
|
.name = "NVENC",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.sid = TEGRA_SID_NVJPG,
|
||
|
|
.noids = 2,
|
||
|
|
.oid = {
|
||
|
|
NVJPGSRD,
|
||
|
|
NVJPGSWR,
|
||
|
|
},
|
||
|
|
.ord = SIM_OVERRIDE,
|
||
|
|
.name = "NVJPG",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_mc_sid_soc_data tegra186_mc_soc_data = {
|
||
|
|
.sid_override_reg = sid_override_reg,
|
||
|
|
.nsid_override_reg = ARRAY_SIZE(sid_override_reg),
|
||
|
|
.sid_to_oids = sid_to_oids,
|
||
|
|
.nsid_to_oids = ARRAY_SIZE(sid_to_oids),
|
||
|
|
.max_oids = MAX_OID,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int tegra186_mc_sid_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
return tegra_mc_sid_probe(pdev, &tegra186_mc_soc_data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id tegra186_mc_sid_of_match[] = {
|
||
|
|
{ .compatible = "nvidia,tegra-mc-sid", },
|
||
|
|
{ .compatible = "nvidia,tegra186-mc-sid", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, tegra186_mc_sid_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver tegra186_mc_sid_driver = {
|
||
|
|
.probe = tegra186_mc_sid_probe,
|
||
|
|
.remove = tegra_mc_sid_remove,
|
||
|
|
.driver = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.name = "tegra186-mc-sid",
|
||
|
|
.of_match_table = of_match_ptr(tegra186_mc_sid_of_match),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init tegra186_mc_sid_init(void)
|
||
|
|
{
|
||
|
|
struct device_node *np;
|
||
|
|
struct platform_device *pdev = NULL;
|
||
|
|
|
||
|
|
np = of_find_compatible_node(NULL, NULL, "nvidia,tegra186-mc-sid");
|
||
|
|
if (!np)
|
||
|
|
np = of_find_compatible_node(NULL, NULL, "nvidia,tegra-mc-sid");
|
||
|
|
|
||
|
|
if (np) {
|
||
|
|
pdev = of_platform_device_create(np, NULL,
|
||
|
|
platform_bus_type.dev_root);
|
||
|
|
of_node_put(np);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IS_ERR_OR_NULL(pdev))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
return platform_driver_register(&tegra186_mc_sid_driver);
|
||
|
|
}
|
||
|
|
arch_initcall(tegra186_mc_sid_init);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("MC StreamID configuration");
|
||
|
|
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>, Pritesh Raithatha <praithatha@nvidia.com>");
|
||
|
|
MODULE_LICENSE("GPL v2");
|