536 lines
13 KiB
C
536 lines
13 KiB
C
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/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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#include <linux/tegra-hsp.h>
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#define HSP_DIMENSIONING 0x380
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#define HSP_DB_REG_TRIGGER 0x0
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#define HSP_DB_REG_ENABLE 0x4
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#define HSP_DB_REG_RAW 0x8
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#define HSP_DB_REG_PENDING 0xc
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enum tegra_hsp_init_status {
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HSP_INIT_PENDING,
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HSP_INIT_FAILED,
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HSP_INIT_OKAY,
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};
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struct hsp_top {
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int status;
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void __iomem *base;
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};
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static DEFINE_SPINLOCK(hsp_top_lock);
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struct db_handler_info {
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db_handler_t handler;
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void *data;
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};
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static struct hsp_top hsp_top = { .status = HSP_INIT_PENDING };
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static void __iomem *db_bases[HSP_NR_DBS];
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static DEFINE_MUTEX(db_handlers_lock);
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static int db_irq;
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static struct db_handler_info db_handlers[HSP_LAST_MASTER + 1];
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static const char * const master_names[] = {
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[HSP_MASTER_SECURE_CCPLEX] = "SECURE_CCPLEX",
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[HSP_MASTER_SECURE_DPMU] = "SECURE_DPMU",
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[HSP_MASTER_SECURE_BPMP] = "SECURE_BPMP",
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[HSP_MASTER_SECURE_SPE] = "SECURE_SPE",
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[HSP_MASTER_SECURE_SCE] = "SECURE_SCE",
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[HSP_MASTER_CCPLEX] = "CCPLEX",
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[HSP_MASTER_DPMU] = "DPMU",
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[HSP_MASTER_BPMP] = "BPMP",
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[HSP_MASTER_SPE] = "SPE",
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[HSP_MASTER_SCE] = "SCE",
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[HSP_MASTER_APE] = "APE",
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};
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static const char * const db_names[] = {
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[HSP_DB_DPMU] = "DPMU",
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[HSP_DB_CCPLEX] = "CCPLEX",
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[HSP_DB_CCPLEX_TZ] = "CCPLEX_TZ",
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[HSP_DB_BPMP] = "BPMP",
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[HSP_DB_SPE] = "SPE",
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[HSP_DB_SCE] = "SCE",
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[HSP_DB_APE] = "APE",
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};
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static inline int is_master_valid(int master)
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{
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return master_names[master] != NULL;
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}
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static inline int next_valid_master(int m)
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{
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for (m++; m <= HSP_LAST_MASTER && !is_master_valid(m); m++)
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;
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return m;
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}
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#define for_each_valid_master(m) \
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for (m = HSP_FIRST_MASTER; \
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m <= HSP_LAST_MASTER; \
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m = next_valid_master(m))
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#define hsp_ready() (hsp_top.status == HSP_INIT_OKAY)
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static inline u32 hsp_readl(void __iomem *base, int reg)
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{
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return readl(base + reg);
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}
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static inline void hsp_writel(void __iomem *base, int reg, u32 val)
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{
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writel(val, base + reg);
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(void)readl(base + reg);
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}
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static irqreturn_t dbell_irq(int irq, void *data)
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{
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ulong reg;
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int master;
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struct db_handler_info *info;
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reg = (ulong)hsp_readl(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_PENDING);
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hsp_writel(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_PENDING, reg);
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for_each_set_bit(master, ®, HSP_LAST_MASTER + 1) {
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info = &db_handlers[master];
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if (unlikely(!is_master_valid(master))) {
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pr_warn("invalid master from HW.\n");
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continue;
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}
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if (info->handler)
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info->handler(info->data);
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}
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return IRQ_HANDLED;
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}
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static int tegra_hsp_db_set_master(enum tegra_hsp_master master, bool enabled)
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{
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unsigned long flags;
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u32 reg;
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if (!hsp_ready() || !is_master_valid(master))
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return -EINVAL;
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spin_lock_irqsave(&hsp_top_lock, flags);
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reg = hsp_readl(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_ENABLE);
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if (enabled)
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reg |= BIT(master);
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else
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reg &= ~BIT(master);
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hsp_writel(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_ENABLE, reg);
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spin_unlock_irqrestore(&hsp_top_lock, flags);
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return 0;
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}
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/**
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* tegra_hsp_db_enable_master: allow <master> to ring CCPLEX
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* @master: HSP master
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*
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* Returns 0 if successful.
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*/
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int tegra_hsp_db_enable_master(enum tegra_hsp_master master)
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{
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return tegra_hsp_db_set_master(master, true);
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}
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EXPORT_SYMBOL(tegra_hsp_db_enable_master);
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/**
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* tegra_hsp_db_disable_master: disallow <master> from ringing CCPLEX
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* @master: HSP master
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*
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* Returns 0 if successful.
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*/
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int tegra_hsp_db_disable_master(enum tegra_hsp_master master)
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{
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return tegra_hsp_db_set_master(master, false);
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}
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EXPORT_SYMBOL(tegra_hsp_db_disable_master);
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/**
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* tegra_hsp_db_ring: ring the <dbell>
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* @dbell: HSP dbell to be rung
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*
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* Returns 0 if successful.
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*/
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int tegra_hsp_db_ring(enum tegra_hsp_doorbell dbell)
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{
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if (!hsp_ready() || dbell >= HSP_NR_DBS)
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return -EINVAL;
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hsp_writel(db_bases[dbell], HSP_DB_REG_TRIGGER, 1);
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return 0;
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}
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EXPORT_SYMBOL(tegra_hsp_db_ring);
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/**
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* tegra_hsp_db_can_ring: check if CCPLEX can ring the <dbell>
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* @dbell: HSP dbell to be checked
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*
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* Returns 1 if CCPLEX can ring <dbell> otherwise 0.
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*/
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int tegra_hsp_db_can_ring(enum tegra_hsp_doorbell dbell)
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{
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int reg;
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if (!hsp_ready() || dbell >= HSP_NR_DBS)
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return 0;
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reg = hsp_readl(db_bases[dbell], HSP_DB_REG_ENABLE);
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return !!(reg & BIT(HSP_MASTER_CCPLEX));
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}
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EXPORT_SYMBOL(tegra_hsp_db_can_ring);
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/**
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* tegra_hsp_db_add_handler: register an CCPLEX doorbell IRQ handler
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* @ master: master id
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* @ handler: IRQ handler
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* @ data: custom data
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*
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* Returns 0 if successful.
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*/
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int tegra_hsp_db_add_handler(int master, db_handler_t handler, void *data)
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{
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if (!handler || !is_master_valid(master))
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return -EINVAL;
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if (unlikely(db_irq <= 0))
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return -ENODEV;
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mutex_lock(&db_handlers_lock);
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if (likely(db_handlers[master].handler != NULL)) {
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mutex_unlock(&db_handlers_lock);
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return -EBUSY;
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}
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disable_irq(db_irq);
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db_handlers[master].handler = handler;
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db_handlers[master].data = data;
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enable_irq(db_irq);
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mutex_unlock(&db_handlers_lock);
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return 0;
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}
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EXPORT_SYMBOL(tegra_hsp_db_add_handler);
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/**
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* tegra_hsp_db_del_handler: unregister an CCPLEX doorbell IRQ handler
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* @handler: IRQ handler
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*
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* Returns 0 if successful.
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*/
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int tegra_hsp_db_del_handler(int master)
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{
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if (!is_master_valid(master))
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return -EINVAL;
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if (unlikely(db_irq <= 0))
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return -ENODEV;
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mutex_lock(&db_handlers_lock);
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WARN_ON(db_handlers[master].handler == NULL);
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disable_irq(db_irq);
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db_handlers[master].handler = NULL;
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db_handlers[master].data = NULL;
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enable_irq(db_irq);
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mutex_unlock(&db_handlers_lock);
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return 0;
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}
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EXPORT_SYMBOL(tegra_hsp_db_del_handler);
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#ifdef CONFIG_DEBUG_FS
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static int hsp_dbg_enable_master_show(void *data, u64 *val)
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{
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*val = hsp_readl(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_ENABLE);
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return 0;
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}
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static int hsp_dbg_enable_master_store(void *data, u64 val)
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{
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if (!is_master_valid((u32)val))
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return -EINVAL;
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return tegra_hsp_db_enable_master((enum tegra_hsp_master)val);
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}
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static int hsp_dbg_ring_store(void *data, u64 val)
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{
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if (val >= HSP_NR_DBS)
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return -EINVAL;
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return tegra_hsp_db_ring((enum tegra_hsp_doorbell)val);
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}
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static int hsp_dbg_can_ring_show(void *data, u64 *val)
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{
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enum tegra_hsp_doorbell db;
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*val = 0ull;
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for (db = HSP_FIRST_DB; db <= HSP_LAST_DB; db++)
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if (tegra_hsp_db_can_ring(db))
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*val |= BIT(db);
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return 0;
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}
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/* By convention, CPU shouldn't touch other processors' DBs.
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* So this interface is created for debugging purpose.
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*/
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static int hsp_dbg_can_ring_store(void *data, u64 val)
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{
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unsigned long flags;
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int reg;
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enum tegra_hsp_doorbell dbell = (int)val;
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if (!hsp_ready() || dbell >= HSP_NR_DBS)
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return -EINVAL;
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spin_lock_irqsave(&hsp_top_lock, flags);
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reg = hsp_readl(db_bases[dbell], HSP_DB_REG_ENABLE);
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reg |= BIT(HSP_MASTER_CCPLEX);
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hsp_writel(db_bases[dbell], HSP_DB_REG_ENABLE, reg);
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spin_unlock_irqrestore(&hsp_top_lock, flags);
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return 0;
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}
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static int hsp_dbg_pending_show(void *data, u64 *val)
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{
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*val = hsp_readl(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_PENDING);
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return 0;
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}
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static int hsp_dbg_pending_store(void *data, u64 val)
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{
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hsp_writel(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_PENDING, (u32)val);
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return 0;
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}
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static int hsp_dbg_raw_show(void *data, u64 *val)
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{
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*val = hsp_readl(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_RAW);
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return 0;
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}
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static int hsp_dbg_raw_store(void *data, u64 val)
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{
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hsp_writel(db_bases[HSP_DB_CCPLEX], HSP_DB_REG_RAW, (u32)val);
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return 0;
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}
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static u32 ccplex_intr_count;
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static void hsp_dbg_db_handler(void *data)
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{
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ccplex_intr_count++;
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}
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static int hsp_dbg_intr_count_show(void *data, u64 *val)
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{
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*val = ccplex_intr_count;
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return 0;
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}
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static int hsp_dbg_intr_count_store(void *data, u64 val)
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{
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ccplex_intr_count = val;
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return 0;
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}
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static int hsp_dbg_doorbells_show(struct seq_file *s, void *data)
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{
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int db;
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seq_printf(s, "%-20s%-10s%-10s\n", "name", "id", "offset");
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seq_printf(s, "--------------------------------------------------\n");
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for (db = HSP_FIRST_DB; db <= HSP_LAST_DB; db++)
|
||
|
|
seq_printf(s, "%-20s%-10d%-10lx\n", db_names[db], db,
|
||
|
|
(uintptr_t)(db_bases[db] - hsp_top.base));
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hsp_dbg_masters_show(struct seq_file *s, void *data)
|
||
|
|
{
|
||
|
|
int m;
|
||
|
|
seq_printf(s, "%-20s%-10s\n", "name", "id");
|
||
|
|
seq_printf(s, "----------------------------------------\n");
|
||
|
|
for_each_valid_master(m)
|
||
|
|
seq_printf(s, "%-20s%-10d\n", master_names[m], m);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hsp_dbg_handlers_show(struct seq_file *s, void *data)
|
||
|
|
{
|
||
|
|
int m;
|
||
|
|
seq_printf(s, "%-20s%-30s\n", "master", "handler");
|
||
|
|
seq_printf(s, "--------------------------------------------------\n");
|
||
|
|
for_each_valid_master(m)
|
||
|
|
seq_printf(s, "%-20s%-30pS\n", master_names[m],
|
||
|
|
db_handlers[m].handler);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(enable_master_fops,
|
||
|
|
hsp_dbg_enable_master_show, hsp_dbg_enable_master_store, "%llx\n");
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(ring_fops,
|
||
|
|
NULL, hsp_dbg_ring_store, "%lld\n");
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(can_ring_fops,
|
||
|
|
hsp_dbg_can_ring_show, hsp_dbg_can_ring_store, "%llx\n");
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(pending_fops,
|
||
|
|
hsp_dbg_pending_show, hsp_dbg_pending_store, "%llx\n");
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(raw_fops,
|
||
|
|
hsp_dbg_raw_show, hsp_dbg_raw_store, "%llx\n");
|
||
|
|
DEFINE_SIMPLE_ATTRIBUTE(intr_count_fops,
|
||
|
|
hsp_dbg_intr_count_show, hsp_dbg_intr_count_store, "%lld\n");
|
||
|
|
|
||
|
|
#define DEFINE_DBG_OPEN(name) \
|
||
|
|
static int hsp_dbg_##name##_open(struct inode *inode, struct file *file) \
|
||
|
|
{ \
|
||
|
|
return single_open(file, hsp_dbg_##name##_show, inode->i_private); \
|
||
|
|
} \
|
||
|
|
static const struct file_operations name##_fops = { \
|
||
|
|
.open = hsp_dbg_##name##_open, \
|
||
|
|
.read = seq_read, \
|
||
|
|
.llseek = seq_lseek, \
|
||
|
|
.release = single_release, \
|
||
|
|
};
|
||
|
|
|
||
|
|
DEFINE_DBG_OPEN(doorbells);
|
||
|
|
DEFINE_DBG_OPEN(masters);
|
||
|
|
DEFINE_DBG_OPEN(handlers);
|
||
|
|
|
||
|
|
struct debugfs_entry {
|
||
|
|
const char *name;
|
||
|
|
const struct file_operations *fops;
|
||
|
|
mode_t mode;
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct debugfs_entry hsp_dbg_attrs[] = {
|
||
|
|
{ "enable_master", &enable_master_fops, S_IRUGO | S_IWUSR },
|
||
|
|
{ "ring", &ring_fops, S_IWUSR },
|
||
|
|
{ "can_ring", &can_ring_fops, S_IRUGO | S_IWUSR },
|
||
|
|
{ "pending", &pending_fops, S_IRUGO | S_IWUSR },
|
||
|
|
{ "raw", &raw_fops, S_IRUGO | S_IWUSR },
|
||
|
|
{ "doorbells", &doorbells_fops, S_IRUGO },
|
||
|
|
{ "masters", &masters_fops, S_IRUGO },
|
||
|
|
{ "handlers", &handlers_fops, S_IRUGO },
|
||
|
|
{ "intr_count", &intr_count_fops, S_IRUGO },
|
||
|
|
{ NULL, NULL, 0 }
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct dentry *hsp_debugfs_root;
|
||
|
|
|
||
|
|
static int debugfs_init(void)
|
||
|
|
{
|
||
|
|
struct dentry *dent;
|
||
|
|
struct debugfs_entry *fent;
|
||
|
|
|
||
|
|
if (!hsp_ready())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
hsp_debugfs_root = debugfs_create_dir("tegra_hsp", NULL);
|
||
|
|
if (IS_ERR_OR_NULL(hsp_debugfs_root))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
fent = hsp_dbg_attrs;
|
||
|
|
while (fent->name) {
|
||
|
|
dent = debugfs_create_file(fent->name, fent->mode,
|
||
|
|
hsp_debugfs_root, NULL, fent->fops);
|
||
|
|
if (IS_ERR_OR_NULL(dent))
|
||
|
|
goto abort;
|
||
|
|
fent++;
|
||
|
|
}
|
||
|
|
|
||
|
|
tegra_hsp_db_add_handler(HSP_MASTER_CCPLEX, hsp_dbg_db_handler, NULL);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
abort:
|
||
|
|
debugfs_remove_recursive(hsp_debugfs_root);
|
||
|
|
return -EFAULT;
|
||
|
|
}
|
||
|
|
late_initcall(debugfs_init);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define NV(prop) "nvidia," prop
|
||
|
|
|
||
|
|
int tegra_hsp_init(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
int irq;
|
||
|
|
struct device_node *np = NULL;
|
||
|
|
void __iomem *base;
|
||
|
|
int ret = -EINVAL;
|
||
|
|
u32 reg;
|
||
|
|
|
||
|
|
if (hsp_ready())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/* Look for TOP0 HSP (the one with the doorbells) */
|
||
|
|
do {
|
||
|
|
np = of_find_compatible_node(np, NULL, NV("tegra186-hsp"));
|
||
|
|
if (np == NULL) {
|
||
|
|
WARN_ON(1);
|
||
|
|
pr_err("tegra-hsp: NV data required.\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq = of_irq_get_byname(np, "doorbell");
|
||
|
|
} while (irq <= 0);
|
||
|
|
|
||
|
|
base = of_iomap(np, 0);
|
||
|
|
if (base == NULL) {
|
||
|
|
pr_err("tegra-hsp: failed to map HSP IO space.\n");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
reg = readl(base + HSP_DIMENSIONING);
|
||
|
|
hsp_top.base = base;
|
||
|
|
|
||
|
|
base += 0x10000; /* skip common regs */
|
||
|
|
base += (reg & 0x000f) << 15; /* skip shared mailboxes */
|
||
|
|
base += ((reg & 0x00f0) >> 4) << 16; /* skip shared semaphores */
|
||
|
|
base += ((reg & 0x0f00) >> 8) << 16; /* skip arbitrated semaphores */
|
||
|
|
|
||
|
|
for (i = HSP_FIRST_DB; i <= HSP_LAST_DB; i++) {
|
||
|
|
db_bases[i] = base;
|
||
|
|
base += 0x100;
|
||
|
|
pr_debug("tegra-hsp: db[%d]: %p\n", i, db_bases[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = request_irq(irq, dbell_irq, IRQF_NO_SUSPEND, "hsp", NULL);
|
||
|
|
if (ret) {
|
||
|
|
pr_err("tegra-hsp: request_irq() failed (%d)\n", ret);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
db_irq = irq;
|
||
|
|
hsp_top.status = HSP_INIT_OKAY;
|
||
|
|
ret = 0;
|
||
|
|
out:
|
||
|
|
of_node_put(np);
|
||
|
|
return ret;
|
||
|
|
}
|