477 lines
11 KiB
C
477 lines
11 KiB
C
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/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <asm/traps.h>
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#include <linux/debugfs.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpu.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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#include <asm/cpu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/tegra-mce.h>
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#include <linux/platform/tegra/ari_mca.h>
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#include <linux/platform/tegra/tegra18_a57_mca.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/tegra-cpu.h>
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static u64 read_cpumerrsr(void)
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{
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u64 reg;
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asm volatile("mrs %0, s3_1_c15_c2_2" : "=r" (reg));
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return reg;
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}
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static void write_cpumerrsr(u64 value)
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{
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asm volatile("msr s3_1_c15_c2_2, %0" : "=r" (value));
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}
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static u64 read_l2merrsr(void)
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{
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u64 reg;
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asm volatile("mrs %0, s3_1_c15_c2_3" : "=r" (reg));
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return reg;
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}
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static void write_l2merrsr(u64 value)
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{
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asm volatile ("msr s3_1_c15_c2_3, %0" : "=r" (value));
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}
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static u64 read_l2ctlr(void)
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{
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u64 reg;
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asm volatile("mrs %0, s3_1_c11_c0_2" : "=r" (reg));
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return reg;
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}
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static int report_serr(int cpu, int uncorrected, int corrected)
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{
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u32 error;
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int e;
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u64 data = 0;
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mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_REPORT_SERR,
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.idx = 0x1,
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.subidx = cpu};
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mca_cmd.inst = uncorrected ? 0x1 : 0;
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mca_cmd.inst |= corrected ? 0x2 : 0;
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e = tegra_mce_read_uncore_mca(mca_cmd, &data, &error);
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if (e != 0) {
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pr_err("%s: ARI call failed\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static void print_a57_serr(struct seq_file *file, const char *fmt, ...)
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{
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va_list args;
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struct va_format vaf;
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va_start(args, fmt);
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if (file) {
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seq_vprintf(file, fmt, args);
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} else {
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vaf.fmt = fmt;
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vaf.va = &args;
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pr_crit("%pV", &vaf);
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}
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va_end(args);
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}
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static struct a57_ramid ramids[] = {
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{.name = "Instruction L1 Tag RAM", .id = 0x00},
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{.name = "Instruction L1 Data RAM", .id = 0x01},
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{.name = "Data L1 Tag RAM", .id = 0x08},
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{.name = "Data L1 Data RAM", .id = 0x09},
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{.name = "L2 TLB RAM", .id = 0x18},
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{}
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};
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static struct a57_ramid l2_ramids[] = {
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{.name = "L2 Tag RAM", .id = 0x10},
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{.name = "L2 Data RAM", .id = 0x11},
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{.name = "L2 Snoop Tag RAM", .id = 0x12},
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{.name = "L2 Dirty RAM", .id = 0x14},
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{.name = "L2 Inclusion PF RAM", .id = 0x18},
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{}
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};
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static void print_ramid(struct seq_file *file, u64 ramid)
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{
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u64 i;
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int found = 0;
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for (i = 0; ramids[i].name; i++) {
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if (ramids[i].id == ramid) {
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print_a57_serr(file, "\t%s: 0x%llx\n",
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ramids[i].name, ramid);
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found = 1;
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break;
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}
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}
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if (!found)
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print_a57_serr(file, "\tUnknown RAMID: 0x%llx\n", ramid);
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}
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static void print_l2ramid(struct seq_file *file, u64 ramid)
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{
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u64 i;
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int found = 0;
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for (i = 0; l2_ramids[i].name; i++) {
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if (l2_ramids[i].id == ramid) {
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print_a57_serr(file, "\t%s: 0x%llx\n",
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l2_ramids[i].name, ramid);
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found = 1;
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break;
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}
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}
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if (!found)
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print_a57_serr(file, "\tUnknown RAMID: 0x%llx\n", ramid);
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}
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static void print_a57_cpumerrsr(struct seq_file *file, u64 syndrome)
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{
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print_a57_serr(file, "\tCPUMERRSR: 0x%llx\n", syndrome);
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if (syndrome & A57_CPUMERRSR_VALID) {
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if (syndrome & A57_CPUMERRSR_FATAL)
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print_a57_serr(file, "\tFATAL Error\n");
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print_ramid(file, get_a57_cpumerrsr_ramid(syndrome));
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print_a57_serr(file, "\tBank/Way of Error: 0x%llx\n",
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get_a57_cpumerrsr_bank(syndrome));
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print_a57_serr(file, "\tIndex of Error: 0x%llx\n",
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get_a57_cpumerrsr_index(syndrome));
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print_a57_serr(file, "\tRepeat Error Count: %llu\n",
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get_a57_cpumerrsr_repeat(syndrome));
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print_a57_serr(file, "\tOther Error Count: %llu\n",
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get_a57_cpumerrsr_other(syndrome));
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}
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}
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static void print_a57_l2merrsr(struct seq_file *file, u64 syndrome)
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{
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print_a57_serr(file, "\tL2MERRSR: 0x%llx\n", syndrome);
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if (syndrome & A57_L2MERRSR_VALID) {
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if (syndrome & A57_L2MERRSR_FATAL)
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print_a57_serr(file, "\tFATAL Error\n");
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print_l2ramid(file, get_a57_l2merrsr_ramid(syndrome));
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print_a57_serr(file, "\tCPU ID of Error: %llu\n",
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get_a57_l2merrsr_cpuid(syndrome));
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print_a57_serr(file, "\tWAY of Error: %llu\n",
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get_a57_l2merrsr_way(syndrome));
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print_a57_serr(file, "\tIndex of Error: %llu\n",
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get_a57_l2merrsr_index(syndrome));
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print_a57_serr(file, "\tRepeat Error Count: %llu\n",
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get_a57_l2merrsr_repeat(syndrome));
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print_a57_serr(file, "\tOther Error Count: %llu\n",
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get_a57_l2merrsr_other(syndrome));
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}
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}
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static void print_a57_merrsr(struct seq_file *file,
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u64 cpu_syndrome, u64 l2_syndrome)
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{
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if (cpu_syndrome & A57_CPUMERRSR_VALID)
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print_a57_cpumerrsr(file, cpu_syndrome);
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if (l2_syndrome & A57_L2MERRSR_VALID)
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print_a57_l2merrsr(file, l2_syndrome);
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}
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static DEFINE_RAW_SPINLOCK(a57_mca_lock);
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static int a57_serr_hook(struct pt_regs *regs, int reason,
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unsigned int esr, void *priv)
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{
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u64 cpu_syndrome;
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u64 l2_syndrome;
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int cpu;
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int cpuid;
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u64 mpidr;
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int corrected;
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unsigned long flags;
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struct cpuinfo_arm64 *cpuinfo;
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int retval = 1;
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raw_spin_lock_irqsave(&a57_mca_lock, flags);
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cpu = smp_processor_id();
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cpuinfo = &per_cpu(cpu_data, cpu);
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if (MIDR_PARTNUM(cpuinfo->reg_midr) == ARM_CPU_PART_CORTEX_A57) {
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cpu_syndrome = read_cpumerrsr();
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l2_syndrome = read_l2merrsr();
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mpidr = read_cpuid_mpidr();
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cpuid = (int)MCA_ARI_EXTRACT(mpidr, 1, 0);
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if ((cpu_syndrome & A57_CPUMERRSR_VALID)
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|| (l2_syndrome & A57_L2MERRSR_VALID)) {
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pr_crit("**************************************\n");
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pr_crit("A57 CPU Memory Error on CPU %d (A57 Core %d)\n",
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cpu, cpuid);
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pr_crit("\tESR: 0x%x\n", esr);
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print_a57_merrsr(NULL, cpu_syndrome, l2_syndrome);
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pr_crit("**************************************\n");
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retval = 0;
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}
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if (cpu_syndrome & A57_CPUMERRSR_VALID) {
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if (cpu_syndrome & A57_CPUMERRSR_FATAL) {
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corrected = (get_a57_cpumerrsr_other(cpu_syndrome) != 0) ||
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(get_a57_cpumerrsr_repeat(cpu_syndrome) != 0);
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report_serr(cpuid,
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1,
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corrected);
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}
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write_cpumerrsr(0x0ULL);
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}
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if (l2_syndrome & A57_L2MERRSR_VALID)
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write_l2merrsr(0x0ULL);
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}
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raw_spin_unlock_irqrestore(&a57_mca_lock, flags);
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return retval;
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}
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static DEFINE_MUTEX(a57_serr_mutex);
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static int a57_merrsr_show(struct seq_file *file, void *data)
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{
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u64 cpu_syndrome;
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u64 l2_syndrome;
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int cpu;
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struct cpuinfo_arm64 *cpuinfo;
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mutex_lock(&a57_serr_mutex);
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cpu = smp_processor_id();
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cpuinfo = &per_cpu(cpu_data, cpu);
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if (MIDR_PARTNUM(cpuinfo->reg_midr) == ARM_CPU_PART_CORTEX_A57) {
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cpu_syndrome = read_cpumerrsr();
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l2_syndrome = read_l2merrsr();
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if ((cpu_syndrome & A57_CPUMERRSR_VALID)
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|| (l2_syndrome & A57_L2MERRSR_VALID)) {
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print_a57_merrsr(file, cpu_syndrome, l2_syndrome);
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if (cpu_syndrome & A57_CPUMERRSR_VALID)
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write_cpumerrsr(0x0ULL);
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if (l2_syndrome & A57_L2MERRSR_VALID)
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write_l2merrsr(0x0ULL);
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} else {
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print_a57_serr(file,
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"CPUMERRSR and L2MERRSR not valid\n");
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}
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} else {
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print_a57_serr(file, "Not running on an A57 CPU\n");
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}
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mutex_unlock(&a57_serr_mutex);
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return 0;
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}
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static u32 cpu_ecc_errs;
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static DEFINE_RAW_SPINLOCK(cpu_ecc_lock);
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static void a57_cpu_ecc_err(void *info)
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{
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int cpu;
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struct cpuinfo_arm64 *cpuinfo;
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u64 cpu_syndrome;
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u64 l2_syndrome;
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unsigned long flags;
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raw_spin_lock_irqsave(&cpu_ecc_lock, flags);
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cpu = smp_processor_id();
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cpuinfo = &per_cpu(cpu_data, cpu);
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cpu_syndrome = read_cpumerrsr();
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l2_syndrome = read_l2merrsr();
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if (cpu_syndrome & A57_CPUMERRSR_VALID) {
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if ((cpu_syndrome & A57_CPUMERRSR_FATAL)
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|| (get_a57_cpumerrsr_repeat(cpu_syndrome) != 0ULL)
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|| (get_a57_cpumerrsr_other(cpu_syndrome) != 0ULL))
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cpu_ecc_errs |= 1U << cpu;
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write_cpumerrsr(0x0ULL);
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}
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if (l2_syndrome & A57_L2MERRSR_VALID) {
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if ((l2_syndrome & A57_L2MERRSR_FATAL)
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|| (get_a57_l2merrsr_repeat(l2_syndrome) != 0ULL)
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|| (get_a57_l2merrsr_other(l2_syndrome) != 0ULL))
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cpu_ecc_errs |= 1U << cpu;
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write_l2merrsr(0x0ULL);
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}
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raw_spin_unlock_irqrestore(&cpu_ecc_lock, flags);
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}
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static int a57_ecc_show(struct seq_file *file, void *data)
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{
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int cpu;
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struct cpuinfo_arm64 *cpuinfo;
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cpu_ecc_errs = 0;
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for_each_online_cpu(cpu) {
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cpuinfo = &per_cpu(cpu_data, cpu);
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if (MIDR_PARTNUM(cpuinfo->reg_midr) == ARM_CPU_PART_CORTEX_A57) {
|
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|
|
smp_call_function_single(cpu, a57_cpu_ecc_err,
|
||
|
|
NULL, true);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
print_a57_serr(file, "0x%08x\n", cpu_ecc_errs);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int a57_merrsr_open(struct inode *inode, struct file *file)
|
||
|
|
{
|
||
|
|
return single_open(file, a57_merrsr_show, inode->i_private);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct file_operations tegra18_a57_merrsr_fops = {
|
||
|
|
.open = a57_merrsr_open,
|
||
|
|
.read = seq_read,
|
||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release
|
||
|
|
};
|
||
|
|
|
||
|
|
static int a57_ecc_open(struct inode *inode, struct file *file)
|
||
|
|
{
|
||
|
|
return single_open(file, a57_ecc_show, inode->i_private);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct file_operations tegra18_a57_ecc_fops = {
|
||
|
|
.open = a57_ecc_open,
|
||
|
|
.read = seq_read,
|
||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef CONFIG_DEBUG_FS
|
||
|
|
static struct dentry *a57_serr_root;
|
||
|
|
static int a57_serr_dbgfs_init(void)
|
||
|
|
{
|
||
|
|
struct dentry *d;
|
||
|
|
|
||
|
|
d = debugfs_create_dir("a57-serr", NULL);
|
||
|
|
if (IS_ERR_OR_NULL(d)) {
|
||
|
|
pr_err("%s: could not create 'a57-serr' node\n", __func__);
|
||
|
|
goto clean;
|
||
|
|
}
|
||
|
|
|
||
|
|
a57_serr_root = d;
|
||
|
|
|
||
|
|
d = debugfs_create_file("a57-merrsr",
|
||
|
|
S_IRUGO, a57_serr_root,
|
||
|
|
NULL,
|
||
|
|
&tegra18_a57_merrsr_fops);
|
||
|
|
if (IS_ERR_OR_NULL(d)) {
|
||
|
|
pr_err("%s: could not create '%s' node\n",
|
||
|
|
__func__, "a57-merrsr");
|
||
|
|
goto clean;
|
||
|
|
}
|
||
|
|
|
||
|
|
d = debugfs_create_file("a57-ecc",
|
||
|
|
S_IRUGO, a57_serr_root,
|
||
|
|
NULL,
|
||
|
|
&tegra18_a57_ecc_fops);
|
||
|
|
if (IS_ERR_OR_NULL(d)) {
|
||
|
|
pr_err("%s: could not create '%s' node\n",
|
||
|
|
__func__, "a57-ecc");
|
||
|
|
goto clean;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
clean:
|
||
|
|
debugfs_remove_recursive(a57_serr_root);
|
||
|
|
return PTR_ERR(d);
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
static int a57_serr_dbgfs_init(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct serr_hook hook = {
|
||
|
|
.fn = a57_serr_hook
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init tegra18_a57_serr_init(void)
|
||
|
|
{
|
||
|
|
int cpu;
|
||
|
|
u32 ecc_settings;
|
||
|
|
unsigned long flags;
|
||
|
|
struct cpuinfo_arm64 *cpuinfo;
|
||
|
|
char *core_type = "Denver";
|
||
|
|
|
||
|
|
if (tegra_get_chip_id() != TEGRA186)
|
||
|
|
return 0;
|
||
|
|
/*
|
||
|
|
* No point in registering an ECC error handler on the
|
||
|
|
* simulator.
|
||
|
|
*/
|
||
|
|
if (tegra_cpu_is_asim())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
raw_spin_lock_irqsave(&a57_mca_lock, flags);
|
||
|
|
cpu = smp_processor_id();
|
||
|
|
cpuinfo = &per_cpu(cpu_data, cpu);
|
||
|
|
|
||
|
|
if (MIDR_PARTNUM(cpuinfo->reg_midr) == ARM_CPU_PART_CORTEX_A57) {
|
||
|
|
ecc_settings = read_l2ctlr();
|
||
|
|
pr_info("**** A57 ECC: %s\n",
|
||
|
|
(ecc_settings & A57_L2CTLR_ECC_EN) ? "Enabled" :
|
||
|
|
"Disabled");
|
||
|
|
core_type = "A57";
|
||
|
|
}
|
||
|
|
|
||
|
|
pr_info("%s: on CPU %d a %s Core\n", __func__, cpu, core_type);
|
||
|
|
raw_spin_unlock_irqrestore(&a57_mca_lock, flags);
|
||
|
|
|
||
|
|
register_serr_hook(&hook);
|
||
|
|
|
||
|
|
return a57_serr_dbgfs_init();
|
||
|
|
}
|
||
|
|
module_init(tegra18_a57_serr_init);
|
||
|
|
|
||
|
|
static void __exit tegra18_a57_serr_exit(void)
|
||
|
|
{
|
||
|
|
unregister_serr_hook(&hook);
|
||
|
|
}
|
||
|
|
module_exit(tegra18_a57_serr_exit);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_DESCRIPTION("Tegra A57 SError handler");
|