398 lines
12 KiB
C
398 lines
12 KiB
C
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/*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Authors:
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* VenkataJagadish.p <vjagadish@nvidia.com>
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* Naveen Kumar Arepalli <naveenk@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _UFS_TEGRA_H
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#define _UFS_TEGRA_H
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#include <linux/io.h>
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#define NV_ADDRESS_MAP_MPHY_L0_BASE 0x02470000
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#define NV_ADDRESS_MAP_MPHY_L1_BASE 0x02480000
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#define NV_ADDRESS_MAP_UFSHC_AUX_BASE 0x02460000
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/*
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* M-PHY Registers
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*/
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#define MPHY_TX_APB_TX_CG_OVR0_0 0x170
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#define MPHY_TX_CLK_EN_SYMB (1 << 1)
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#define MPHY_TX_CLK_EN_SLOW (1 << 3)
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#define MPHY_TX_CLK_EN_FIXED (1 << 4)
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#define MPHY_TX_CLK_EN_3X (1 << 5)
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#define MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 0x34
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#define TX_ADVANCED_GRANULARITY (0x8 << 16)
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#define TX_ADVANCED_GRANULARITY_SETTINGS (0x1 << 8)
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#define MPHY_GO_BIT 1
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#define MPHY_TX_APB_TX_VENDOR0_0 0x100
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#define MPHY_RX_APB_CAPABILITY_88_8B_0 0x88
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#define RX_HS_G1_SYNC_LENGTH_CAPABILITY(x) (((x) & 0x3f) << 24)
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#define RX_HS_SYNC_LENGTH 0xf
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#define MPHY_RX_APB_CAPABILITY_94_97_0 0x94
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#define RX_HS_G2_SYNC_LENGTH_CAPABILITY(x) (((x) & 0x3f) << 0)
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#define RX_HS_G3_SYNC_LENGTH_CAPABILITY(x) (((x) & 0x3f) << 8)
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#define MPHY_RX_APB_CAPABILITY_8C_8F_0 0x8c
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#define RX_MIN_ACTIVATETIME_CAP(x) (((x) & 0xf) << 24)
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#define RX_MIN_ACTIVATETIME 0x5
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#define MPHY_RX_APB_CAPABILITY_98_9B_0 0x98
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#define RX_ADVANCED_FINE_GRANULARITY(x) (((x) & 0x1) << 0)
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#define RX_ADVANCED_GRANULARITY(x) (((x) & 0x3) << 1)
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#define RX_ADVANCED_MIN_ACTIVATETIME(x) (((x) & 0xf) << 16)
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#define RX_ADVANCED_MIN_AT 0xa
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#define MPHY_RX_APB_VENDOR2_0 0x184
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#define MPHY_RX_APB_VENDOR2_0_RX_CAL_EN (1 << 15)
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#define MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE (1 << 19)
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/* Unipro Vendor registers */
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/*
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+ * Vendor Specific Attributes
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+ */
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#define VS_DEBUGSAVECONFIGTIME 0xD0A0
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#define VS_DEBUGSAVECONFIGTIME_TREF 0x6
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#define SET_TREF(x) (((x) & 0x7) << 2)
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#define VS_DEBUGSAVECONFIGTIME_ST_SCT 0x3
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#define SET_ST_SCT(x) ((x) & 0x3)
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#define VS_TXBURSTCLOSUREDELAY 0xD084
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#define MPHY_ADDR_RANGE 0x1fc
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#define UFS_AUX_ADDR_RANGE 0x18
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/*UFS Clock Defines*/
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#define UFSHC_CLK_FREQ 204000000
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#define UFSDEV_CLK_FREQ 19200000
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/*Uphy pll clock defines*/
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#define UFS_CLK_UPHY_PLL3_RATEA 4992000000
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#define UFS_CLK_UPHY_PLL3_RATEB 5840000000
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enum ufs_state {
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UFSHC_INIT,
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UFSHC_SUSPEND,
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UFSHC_RESUME,
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};
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/* vendor specific pre-defined parameters */
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/*
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* HCLKFrequency in MHz.
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* HCLKDIV is used to generate 1usec tick signal used by Unipro.
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*/
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#define UFS_VNDR_HCLKDIV_1US_TICK 0xCC
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/*UFS host controller vendor specific registers */
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enum {
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REG_UFS_VNDR_HCLKDIV = 0xFC,
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};
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/*
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* UFS AUX Registers
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*/
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#define UFSHC_AUX_UFSHC_STATUS_0 0x10
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#define UFSHC_HIBERNATE_STATUS (1 << 0)
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#define UFSHC_AUX_UFSHC_DEV_CTRL_0 0x14
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#define UFSHC_DEV_CLK_EN (1 << 0)
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#define UFSHC_DEV_RESET (1 << 1)
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#define UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0 0x08
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#define UFSHC_CLK_OVR_ON (1 << 0)
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#define UFSHC_HCLK_OVR_ON (1 << 1)
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#define UFSHC_LP_CLK_T_CLK_OVR_ON (1 << 2)
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#define UFSHC_CLK_T_CLK_OVR_ON (1 << 3)
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#define UFSHC_CG_SYS_CLK_OVR_ON (1 << 4)
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#define UFSHC_TX_SYMBOL_CLK_OVR_ON (1 << 5)
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#define UFSHC_RX_SYMBOLCLKSELECTED_CLK_OVR_ON (1 << 6)
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#define UFSHC_PCLK_OVR_ON (1 << 7)
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/*
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* MPHY Context save armphy_rx_apb registers
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*/
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static u16 __attribute__ ((unused)) mphy_rx_apb[] = {
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0x080, /* MPHY_RX_APB_CAPABILITY_80_83_0 */
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0x084, /* MPHY_RX_APB_CAPABILITY_84_87_0 */
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0x088, /* MPHY_RX_APB_CAPABILITY_88_8B_0 */
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0x08c, /* MPHY_RX_APB_CAPABILITY_8C_8F_0 */
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0x090, /* MPHY_RX_APB_CAPABILITY_90_93_0 */
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0x094, /* MPHY_RX_APB_CAPABILITY_94_97_0 */
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0x098, /* MPHY_RX_APB_CAPABILITY_98_9B_0 */
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0x0a0, /* MPHY_RX_APB_ATTRIBUTE_A0_A3_0 */
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0x0a4, /* MPHY_RX_APB_ATTRIBUTE_A4_A7_0 */
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0x0a8, /* MPHY_RX_APB_ATTRIBUTE_A8_AB_0 */
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0x0d0, /* MPHY_RX_APB_MC_STATUS_D0_D3_0 */
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0x0d4, /* MPHY_RX_APB_MC_STATUS_D4_D7_0 */
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0x0d8, /* MPHY_RX_APB_MC_STATUS_D8_DB_0 */
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0x0dc, /* MPHY_RX_APB_MC_STATUS_DC_DF_0 */
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0x0e0, /* MPHY_RX_APB_MC_STATUS_E0_E3_0 */
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0x0e4, /* MPHY_RX_APB_MC_STATUS_E4_E7_0 */
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0x180, /* MPHY_RX_APB_VENDOR1_0 */
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0x184, /* MPHY_RX_APB_VENDOR2_0 */
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0x188, /* MPHY_RX_APB_VENDOR3_0 */
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0x18c, /* MPHY_RX_APB_VENDOR4_0 */
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0x190, /* MPHY_RX_APB_VENDOR5_0 */
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0x194, /* MPHY_RX_APB_VENDOR6_0 */
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0x198, /* MPHY_RX_APB_VENDOR7_0 */
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0x19c, /* MPHY_RX_APB_VENDOR8_0 */
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0x1a0, /* MPHY_RX_APB_VENDOR9_0 */
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0x1a4, /* MPHY_RX_APB_VENDOR10_0 */
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0x1a8, /* MPHY_RX_APB_VENDOR11_0 */
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0x1ac, /* MPHY_RX_APB_VENDOR12_0 */
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0x1b0, /* MPHY_RX_APB_VENDOR13_0 */
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0x1b4, /* MPHY_RX_APB_VENDOR14_0 */
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0x1b8, /* MPHY_RX_APB_VENDOR15_0 */
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0x1bc, /* MPHY_RX_APB_VENDOR16_0 */
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0x1c0, /* MPHY_RX_APB_VENDOR17_0 */
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0x1c4, /* MPHY_RX_APB_VENDOR18_0 */
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0x1c8, /* MPHY_RX_APB_VENDOR19_0 */
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0x1cc, /* MPHY_RX_APB_VENDOR20_0 */
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0x1d0, /* MPHY_RX_APB_VENDOR21_0 */
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0x1d4, /* MPHY_RX_APB_VENDOR22_0 */
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0x1d8, /* MPHY_RX_APB_VENDOR23_0 */
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0x1dc, /* MPHY_RX_APB_VENDOR24_0 */
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0x1e0, /* MPHY_RX_APB_VENDOR25_0 */
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0x1e4, /* MPHY_RX_APB_VENDOR26_0 */
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0x1e8, /* MPHY_RX_APB_VENDOR27_0 */
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0x1ec, /* MPHY_RX_APB_VENDOR28_0 */
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0x1f0, /* MPHY_RX_APB_VENDOR29_0 */
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0x1f4, /* MPHY_RX_APB_VENDOR30_0 */
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0x1f8, /* MPHY_RX_APB_VENDOR31_0 */
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0x1fc /* MPHY_RX_APB_VENDOR32_0 */
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};
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/*
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* MPHY Context save armphy_tx_apb registers
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*/
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static u16 __attribute__ ((unused)) mphy_tx_apb[] = {
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0x000, /* MPHY_TX_APB_TX_CAPABILITY_00_03_0 */
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0x004, /* MPHY_TX_APB_TX_CAPABILITY_04_07_0 */
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0x008, /* MPHY_TX_APB_TX_CAPABILITY_08_0B_0 */
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0x00c, /* MPHY_TX_APB_TX_CAPABILITY_0C_0F_0 */
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0x010, /* MPHY_TX_APB_TX_CAPABILITY_10_13_0 */
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0x020, /* MPHY_TX_APB_TX_ATTRIBUTE_20_23_0 */
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0x024, /* MPHY_TX_APB_TX_ATTRIBUTE_24_27_0 */
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0x028, /* MPHY_TX_APB_TX_ATTRIBUTE_28_2B_0 */
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0x02c, /* MPHY_TX_APB_TX_ATTRIBUTE_2C_2F_0 */
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0x030, /* MPHY_TX_APB_TX_ATTRIBUTE_30_33_0 */
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0x034, /* MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 */
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0x038, /* MPHY_TX_APB_TX_ATTRIBUTE_38_3B_0 */
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0x060, /* MPHY_TX_APB_MC_ATTRIBUTE_60_63_0 */
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0x064, /* MPHY_TX_APB_MC_ATTRIBUTE_64_67_0 */
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0x100, /* MPHY_TX_APB_TX_VENDOR0_0 */
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0x104, /* MPHY_TX_APB_TX_VENDOR1_0 */
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0x108, /* MPHY_TX_APB_TX_VENDOR2_0 */
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0x10c, /* MPHY_TX_APB_TX_VENDOR3_0 */
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0x110, /* MPHY_TX_APB_TX_VENDOR4_0 */
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0x114, /* MPHY_TX_APB_TX_VENDOR5_0 */
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0x118, /* MPHY_TX_APB_TX_VENDOR6_0 */
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0x11c, /* MPHY_TX_APB_TX_VENDOR7_0 */
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0x120, /* MPHY_TX_APB_PAD_TIMING0_0 */
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0x124, /* MPHY_TX_APB_PAD_TIMING1_0 */
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0x128, /* MPHY_TX_APB_PAD_TIMING2_0 */
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0x12c, /* MPHY_TX_APB_PAD_TIMING3_0 */
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0x130, /* MPHY_TX_APB_PAD_TIMING4_0 */
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0x134, /* MPHY_TX_APB_PAD_TIMING5_0 */
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0x138, /* MPHY_TX_APB_PAD_TIMING6_0 */
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0x13c, /* MPHY_TX_APB_PAD_TIMING7_0 */
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0x140, /* MPHY_TX_APB_PAD_TIMING8_0 */
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0x144, /* MPHY_TX_APB_PAD_TIMING9_0 */
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0x148, /* MPHY_TX_APB_PAD_TIMING10_0 */
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0x14c, /* MPHY_TX_APB_TX_PAD_OVR_VAL0_0 */
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0x150, /* MPHY_TX_APB_TX_PAD_OVR_CTRL0_0 */
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0x154, /* MPHY_TX_APB_TX_OVR_CTRL0_0 */
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0x158, /* MPHY_TX_APB_TX_OVR_VAL0_0 */
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0x15c, /* MPHY_TX_APB_PAD_TIMER0_0 */
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0x160, /* MPHY_TX_APB_TX_CLK_CTRL0_0 */
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0x164, /* MPHY_TX_APB_TX_CLK_CTRL1_0 */
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0x168, /* MPHY_TX_APB_TX_CLK_CTRL2_0 */
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0x16c, /* MPHY_TX_APB_TX_CLK_CTRL3_0 */
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0x170, /* MPHY_TX_APB_TX_CG_OVR0_0 */
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0x174, /* MPHY_TX_APB_TX_CG_COUNTER0_0 */
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0x178, /* MPHY_TX_APB_TX_PAD_OVR_VAL1_0 */
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0x17c /* MPHY_TX_APB_TX_PAD_OVR_CTRL1_0 */
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};
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struct ufs_tegra_host {
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struct ufs_hba *hba;
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bool is_lane_clks_enabled;
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bool x2config;
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bool enable_mphy_rx_calib;
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bool enable_hs_mode;
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bool enable_ufs_provisioning;
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u32 max_hs_gear;
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bool mask_fast_auto_mode;
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bool mask_hs_mode_b;
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bool configure_uphy_pll3;
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u32 max_pwm_gear;
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enum ufs_state ufshc_state;
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void *mphy_context;
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void __iomem *mphy_l0_base;
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void __iomem *mphy_l1_base;
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void __iomem *ufs_aux_base;
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struct reset_control *ufs_rst;
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struct reset_control *ufs_axi_m_rst;
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struct reset_control *ufshc_lp_rst;
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struct reset_control *mphy_l0_rx_rst;
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struct reset_control *mphy_l0_tx_rst;
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struct reset_control *mphy_l1_rx_rst;
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struct reset_control *mphy_l1_tx_rst;
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struct reset_control *mphy_clk_ctl_rst;
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struct clk *mphy_core_pll_fixed;
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struct clk *mphy_l0_tx_symb;
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struct clk *mphy_tx_1mhz_ref;
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struct clk *mphy_l0_rx_ana;
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struct clk *mphy_l0_rx_symb;
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struct clk *mphy_l0_tx_ls_3xbit;
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struct clk *mphy_l0_rx_ls_bit;
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struct clk *mphy_l1_rx_ana;
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struct clk *mphy_force_ls_mode;
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struct clk *ufshc_parent;
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struct clk *ufsdev_parent;
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struct clk *ufshc_clk;
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struct clk *ufsdev_ref_clk;
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struct clk *ufs_uphy_pll3;
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struct regulator *vddio_ufs;
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struct regulator *vddio_ufs_ap;
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struct pinctrl *ufs_pinctrl;
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struct pinctrl_state *dpd_enable;
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|
struct pinctrl_state *dpd_disable;
|
||
|
|
u32 vs_burst;
|
||
|
|
/* Hibernate entry support is broken
|
||
|
|
WAR is suggested to fix hibernate entry functionality
|
||
|
|
*/
|
||
|
|
#define NVQUIRK_BROKEN_HIBERN8_ENTRY UFS_BIT(0)
|
||
|
|
|
||
|
|
/* UFS tegra deviations from standard UFSHCI spec. */
|
||
|
|
unsigned int nvquirks;
|
||
|
|
bool cd_wakeup_capable;
|
||
|
|
int cd_gpio;
|
||
|
|
unsigned int cd_irq;
|
||
|
|
bool wake_enable_failed;
|
||
|
|
struct delayed_work detect;
|
||
|
|
struct gpio_desc *cd_gpio_desc;
|
||
|
|
bool enable_scramble;
|
||
|
|
#ifdef CONFIG_DEBUG_FS
|
||
|
|
u32 refclk_value;
|
||
|
|
long program_refclk;
|
||
|
|
u32 bootlun_en_id;
|
||
|
|
long program_bootlun_en_id;
|
||
|
|
u32 boot_enable;
|
||
|
|
u32 descr_access_en;
|
||
|
|
u8 *lun_desc_buf;
|
||
|
|
long program_lun;
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
extern struct ufs_hba_variant_ops ufs_hba_tegra_vops;
|
||
|
|
extern int ufshcd_rescan(struct ufs_hba *hb);
|
||
|
|
void ufs_rescan(struct work_struct *work);
|
||
|
|
|
||
|
|
static inline u32 mphy_readl(void __iomem *mphy_base, u32 offset)
|
||
|
|
{
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
val = readl(mphy_base + offset);
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void mphy_writel(void __iomem *mphy_base, u32 val, u32 offset)
|
||
|
|
{
|
||
|
|
writel(val, mphy_base + offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void mphy_update(void __iomem *mphy_base, u32 val,
|
||
|
|
u32 offset)
|
||
|
|
{
|
||
|
|
u32 update_val;
|
||
|
|
|
||
|
|
update_val = mphy_readl(mphy_base, offset);
|
||
|
|
update_val |= val;
|
||
|
|
mphy_writel(mphy_base, update_val, offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 ufs_aux_readl(void __iomem *ufs_aux_base, u32 offset)
|
||
|
|
{
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
val = readl(ufs_aux_base + offset);
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ufs_aux_writel(void __iomem *ufs_aux_base, u32 val,
|
||
|
|
u32 offset)
|
||
|
|
{
|
||
|
|
writel(val, ufs_aux_base + offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ufs_aux_update(void __iomem *ufs_aux_base, u32 val,
|
||
|
|
u32 offset)
|
||
|
|
{
|
||
|
|
u32 update_val;
|
||
|
|
|
||
|
|
update_val = ufs_aux_readl(ufs_aux_base, offset);
|
||
|
|
update_val |= val;
|
||
|
|
ufs_aux_writel(ufs_aux_base, update_val, offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ufs_aux_clear_bits(void __iomem *ufs_aux_base, u32 val,
|
||
|
|
u32 offset)
|
||
|
|
{
|
||
|
|
u32 update_val;
|
||
|
|
|
||
|
|
update_val = ufs_aux_readl(ufs_aux_base, offset);
|
||
|
|
update_val &= ~val;
|
||
|
|
ufs_aux_writel(ufs_aux_base, update_val, offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ufs_save_regs(void __iomem *reg_base, u32 *save_addr,
|
||
|
|
u16 reg_array[], u32 no_of_regs)
|
||
|
|
{
|
||
|
|
u32 regs;
|
||
|
|
u32 *dest = save_addr;
|
||
|
|
|
||
|
|
for (regs = 0; regs < no_of_regs; ++regs, ++dest)
|
||
|
|
*dest = readl(reg_base + (u32)reg_array[regs]);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ufs_restore_regs(void __iomem *reg_base, u32 *save_addr,
|
||
|
|
u16 reg_array[], u32 no_of_regs)
|
||
|
|
{
|
||
|
|
u32 regs;
|
||
|
|
u32 *src = save_addr;
|
||
|
|
|
||
|
|
for (regs = 0; regs < no_of_regs; ++regs, ++src)
|
||
|
|
writel(*src, reg_base + (u32)reg_array[regs]);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|