106 lines
4.9 KiB
C
106 lines
4.9 KiB
C
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/*
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* tc358770_dsi2edp.h: dsi-edp controller tc358770 driver headers.
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*
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* Copyright (c) 2012-2018, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_TC358770_DSI2EDP_H
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#define __DRIVERS_VIDEO_TEGRA_DC_TC358770_DSI2EDP_H
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struct tegra_dc_dsi2edp_data {
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struct tegra_dc_dsi_data *dsi;
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struct i2c_client *client_i2c;
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struct regmap *regmap;
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struct tegra_dc_mode *mode;
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bool dsi2edp_enabled;
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struct mutex lock;
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};
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#define TC358770_DATA0_DPHY_TX_CTRL 0x0004
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#define TC358770_CLOCK_DPHY_RX_CTRL 0x0020
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#define TC358770_DATA3W_CTRL 0x0050
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#define TC358770_DSI0_PPI_START 0x0104
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#define TC358770_DSI0_PPI_LPTXTIMECNT 0x0114
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#define TC358770_DSI0_PPI_LANEENABLE 0x0134
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#define TC358770_DSI0_PPI_TX_RX_TA 0x013C
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#define TC358770_PPI_CLS_ANALOG_TMR 0x0140
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#define TC358770_PPI_D0S_ANALOG_TMR 0x0144
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#define TC358770_PPI_D1S_ANALOG_TMR 0x0148
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#define TC358770_PPI_D2S_ANALOG_TMR 0x014C
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#define TC358770_PPI_D3S_ANALOG_TMR 0x0150
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#define TC358770_DSI0_PPI_D0S_CLRSIPOCOUNT 0x0164
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#define TC358770_DSI0_PPI_D1S_CLRSIPOCOUNT 0x0168
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#define TC358770_DSI0_PPI_D2S_CLRSIPOCOUNT 0x016C
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#define TC358770_DSI0_PPI_D3S_CLRSIPOCOUNT 0x0170
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#define TC358770_DSI0_DSI_START 0x0204
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#define TC358770_DSI0_DSI_LANEENABLE 0x0210
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#define TC358770_DSI_LANESTATUS0 0x0214
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#define TC358770_DSI_LANESTATUS1 0x0218
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#define TC358770_DSI_INTERRUPT_STATUS 0x0220
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#define TC358770_DSI_INTERRUPT_CLEAR 0x0228
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#define TC358770_VIDEO_FRAME_CTRL 0x0450
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#define TC358770_HORIZONTAL_TIME0 0x0454
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#define TC358770_HORIZONTAL_TIME1 0x0458
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#define TC358770_VERTICAL_TIME0 0x045C
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#define TC358770_VERTICAL_TIME1 0x0460
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#define TC358770_VIDEO_FRAME_UPDATE_ENABLE 0x0464
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#define TC358770_CMD_CTRL 0x0480
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#define TC358770_LR_SIZE 0x0484
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#define TC358770_PG_SIZE 0x0488
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#define TC358770_RM_PXL 0x048C
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#define TC358770_HORI_SCLR_HCOEF 0x0490
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#define TC358770_HORI_SCLR_LCOEF 0x0494
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#define TC358770_CHIP_ID 0x0500
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#define TC358770_SYSTEM_CTRL 0x0510
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#define TC358770_DP_CTRL 0x0600
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#define TC358770_NVALUE_VIDEO_CLK_REGEN 0x0614
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#define TC358770_MVALUE_AUDIO_CLK 0x0628
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#define TC358770_NVALUE_AUDIO_CLK_REGEN 0x062C
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#define TC358770_VIDEO_FRAME_OUTPUT_DELAY 0x0644
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#define TC358770_VIDEO_FRAME_SIZE 0x0648
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#define TC358770_VIDEO_FRAME_START 0x064C
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#define TC358770_VIDEO_FRAME_ACTIVE_REGION_SIZE 0x0650
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#define TC358770_VIDEO_FRAME_SYNC_WIDTH 0x0654
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#define TC358770_DP_CONFIG 0x0658
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#define TC358770_AUX_CHANNEL_CONFIG0 0x0660
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#define TC358770_AUX_CHANNEL_CONFIG1 0x0664
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#define TC358770_AUX_CHANNEL_DPCD_ADDR 0x0668
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#define TC358770_AUX_CHANNEL_DPCD_WR_DATA0 0x066C
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#define TC358770_AUX_CHANNEL_DPCD_RD_DATA0 0x067C
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#define TC358770_AUX_CHANNEL_DPCD_RD_DATA1 0x0680
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#define TC358770_AUX_CHANNEL_STATUS 0x068C
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#define TC358770_LINK_TRAINING_CTRL 0x06A0
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#define TC358770_LINK_TRAINING_LOOP_CTRL 0x06D8
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#define TC358770_LINK_TRAINING_STATUS 0x06D0
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#define TC358770_LINK_TRAINING_SINK_CONFIG 0x06E4
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#define TC358770_PHY_CTRL 0x0800
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#define TC358770_LINK_CLK_PLL_CTRL 0x0900
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#define TC358770_STREAM_CLK_PLL_CTRL 0x0908
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#define TC358770_STREAM_CLK_PLL_PARAM 0x0914
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#define TC358770_SYSTEM_CLK_PARAM 0x0918
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#define TC358770_DSI1_PPI_START 0x1104
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#define TC358770_DSI1_PPI_LPTXTIMECNT 0x1114
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#define TC358770_DSI1_PPI_LANEENABLE 0x1134
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#define TC358770_DSI1_PPI_TX_RX_TA 0x113C
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#define TC358770_DSI1_PPI_D0S_CLRSIPOCOUNT 0x1164
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#define TC358770_DSI1_PPI_D1S_CLRSIPOCOUNT 0x1168
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#define TC358770_DSI1_PPI_D2S_CLRSIPOCOUNT 0x116C
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#define TC358770_DSI1_PPI_D3S_CLRSIPOCOUNT 0x1170
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#define TC358770_DSI1_DSI_START 0x1204
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#define TC358770_DSI1_DSI_LANEENABLE 0x1210
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#endif
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