454 lines
18 KiB
C
454 lines
18 KiB
C
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/*
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* dp.h: tegra dp driver.
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*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVER_VIDEO_TEGRA_DC_DP_H__
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#define __DRIVER_VIDEO_TEGRA_DC_DP_H__
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include <linux/tegra_prod.h>
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#include "sor.h"
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#include "dc_priv.h"
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#include "dpaux_regs.h"
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#include "hpd.h"
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#include "../../../../arch/arm/mach-tegra/iomap.h"
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#include "dp_lt.h"
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#ifdef CONFIG_DEBUG_FS
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#include "dp_debug.h"
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extern struct tegra_dp_test_settings default_dp_test_settings;
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#endif
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#define TEGRA_NVHDCP_MAX_DEVS 127
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#define DP_POWER_ON_MAX_TRIES 3
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#define DP_CLOCK_RECOVERY_MAX_TRIES 7
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#define DP_CLOCK_RECOVERY_TOT_TRIES 15
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/*
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* After hpd irq event, source must start
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* reading dpdc offset 200h-205h within
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* 100ms of rising edge hpd
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*/
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#define HPD_IRQ_EVENT_TIMEOUT_MS 70
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/* the +10ms is the time for power rail going up from 10-90% or
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90%-10% on powerdown */
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/* Time from power-rail is turned on and aux/12c-over-aux is available */
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#define EDP_PWR_ON_TO_AUX_TIME_MS (200+10)
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/* Time from power-rail is turned on and MainLink is available for LT */
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#define EDP_PWR_ON_TO_ML_TIME_MS (200+10)
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/* Time from turning off power to turn-it on again (does not include post
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poweron time) */
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#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10)
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/*
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* Receiver capability fields extend from 0 - 0x11fh.
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* By default we read only more useful fields(offsets 0 - 0xb) as
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* required by CTS.
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*/
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#define DP_DPCD_SINK_CAP_SIZE (0xc)
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struct tegra_dc_dp_data {
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/*
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* The following "dpaux" and "sor" fields need to stay at the top of
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* this struct. The placement of these fields needs to align with the
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* tegra_hdmi struct definition in order to support dynamic SOR
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* re-assignment with fakeDP. This is something that needs to be fixed,
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* though.
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*/
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struct tegra_dc_dpaux_data *dpaux;
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struct tegra_dc_sor_data *sor;
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void *out_data;
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void *hda_handle;
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struct tegra_dc *dc;
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u32 irq;
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struct clk *parent_clk; /* pll_dp clock */
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u8 revision;
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struct tegra_dc_mode *mode;
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struct tegra_dc_dp_link_config link_cfg;
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struct tegra_dc_dp_link_config max_link_cfg;
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u8 typec_lane_count; /* # of lanes reported by extcon (Type-C) */
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/*
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* In certain cases, the CCG4 USB-C controller might have already
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* negotiated Alt Mode before the ucsi_ccg kernel driver is initialized.
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* These cases can typically occur when the downstream USB-C partner is
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* connected before ucsi_ccg init (e.g., seamless display). If Alt Mode
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* has been established before ucsi_ccg init, ucsi_ccg has no way to
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* determine what the current lane configuration is since the relevant
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* VDMs (Vendor Defined Messages) have already been sent and received,
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* and ucsi_ccg will not trigger any extcon notifications until the next
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* USB-C configuration change is requested.
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*
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* In order to alleviate the above cases, we'll introduce two flags:
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* - "typec_notified_once" indicates whether the DP driver has received
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* at least one extcon notification from ucsi_ccg so far. Once this
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* flag is set, it will remain set from that point on.
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* - "typec_timed_out_once" indicates whether the DP driver has timed
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* out at least once while waiting for an extcon notification during
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* HPD_PLUG processing. Once this flag is set, it will remain set from
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* that point on.
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*
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* If "typec_notified_once" is FALSE and "typec_timed_out_once" is TRUE,
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* the DP driver will skip all extcon waits during subsequent HPD_PLUG
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* events until it receives at least one extcon notification. This logic
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* is hacky, but is specifically meant to prevent the DP driver from
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* continually timing out during each subsequent HPD_PLUG event before
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* the next configuration change.
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*/
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bool typec_notified_once;
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bool typec_timed_out_once;
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struct tegra_dp_lt_data lt_data;
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bool enabled; /* Controller ready. LT not yet initiated. */
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bool suspended;
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int test_max_lanes; /* Test maximum cfg settings */
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int test_max_link_bw;
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u8 edid_src;
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struct tegra_hpd_data hpd_data;
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#ifdef CONFIG_SWITCH
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struct switch_dev audio_switch;
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#endif
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char *hpd_switch_name;
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char *audio_switch_name;
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struct delayed_work irq_evt_dwork;
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struct tegra_dphdcp *dphdcp;
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struct completion hpd_plug;
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struct tegra_dp_out_ops *out_ops;
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struct tegra_dp_out *pdata;
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struct tegra_prod *prod_list;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugdir;
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#endif
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u8 sink_cap[DP_DPCD_SINK_CAP_SIZE];
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bool sink_cap_valid;
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u8 sink_cnt_cp_ready;
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u16 dpaux_i2c_dbg_addr;
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u32 dpaux_i2c_dbg_num_bytes;
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u16 dpaux_dpcd_dbg_addr;
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u32 dpaux_dpcd_dbg_num_bytes;
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bool early_enable;
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#ifdef CONFIG_DEBUG_FS
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struct tegra_dp_test_settings test_settings;
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};
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extern const struct file_operations test_settings_fops;
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#else
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};
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#endif
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struct tegra_dp_out_ops {
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/* initialize output */
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int (*init)(struct tegra_dc_dp_data *);
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/* destroy output */
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void (*destroy)(struct tegra_dc_dp_data *);
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/* enable output */
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int (*enable)(struct tegra_dc_dp_data *);
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/* disable output */
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void (*disable)(struct tegra_dc_dp_data *);
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/* suspend output */
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void (*suspend)(struct tegra_dc_dp_data *);
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/* resume output */
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void (*resume)(struct tegra_dc_dp_data *);
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/* output postpoweron, called at the end of dc out_ops postpoweron.
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* usually used for bridge devices.
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*/
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void (*postpoweron)(struct tegra_dc_dp_data *);
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};
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#if defined(CONFIG_TEGRA_EDP2LVDS_PS8625)
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extern struct tegra_dp_out_ops tegra_edp2lvds_ops;
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#else
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#define tegra_edp2lvds_ops (*(struct tegra_dp_out_ops *)NULL)
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#endif
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enum {
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VSC_RGB = 0,
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VSC_YUV444 = 1,
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VSC_YUV422 = 2,
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VSC_YUV420 = 3,
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VSC_YONLY = 4,
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VSC_RAW = 5,
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};
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enum {
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VSC_VESA_RANGE = 0,
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VSC_CEA_RANGE = 1,
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};
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enum {
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VSC_6BPC = 0,
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VSC_8BPC = 1,
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VSC_10BPC = 2,
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VSC_12BPC = 3,
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VSC_16BPC = 4,
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};
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enum {
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VSC_RGB_SRGB = 0,
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VSC_RGB_ADOBERGB = 3,
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};
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enum {
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VSC_YUV_ITU_R_BT601 = 0,
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VSC_YUV_ITU_R_BT709 = 1,
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VSC_YUV_XVYCC601 = 2,
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VSC_YUV_XVYCC709 = 3,
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VSC_YUV_SYCC601 = 4,
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VSC_YUV_ADOBEYCC601 = 5,
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};
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enum {
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VSC_CONTENT_TYPE_DEFAULT = 0,
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VSC_CONTENT_TYPE_GRAPHICS = 1,
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VSC_CONTENT_TYPE_PHOTO = 2,
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VSC_CONTENT_TYPE_VIDEO = 3,
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VSC_CONTENT_TYPE_GAME = 4,
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};
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int tegra_dp_dpcd_write_field(struct tegra_dc_dp_data *dp, u32 cmd,
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u8 mask, u8 data);
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void tegra_dc_dp_pre_disable_link(struct tegra_dc_dp_data *dp);
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void tegra_dc_dp_disable_link(struct tegra_dc_dp_data *dp, bool powerdown);
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void tegra_dc_dp_enable_link(struct tegra_dc_dp_data *dp);
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void tegra_dp_update_link_config(struct tegra_dc_dp_data *dp);
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int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, u8 *data_ptr);
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int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd, u8 data);
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void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes);
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bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
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const struct tegra_dc_mode *mode,
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struct tegra_dc_dp_link_config *cfg);
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int tegra_dc_dp_read_ext_dpcd_caps(struct tegra_dc_dp_data *dp,
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struct tegra_dc_dp_ext_dpcd_caps *ext_caps);
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static inline void *tegra_dp_get_outdata(struct tegra_dc_dp_data *dp)
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{
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return dp->out_data;
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}
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static inline void tegra_dp_set_outdata(struct tegra_dc_dp_data *dp,
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void *data)
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{
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dp->out_data = data;
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}
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/* DPCD definitions */
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#define NV_DPCD_REV (0x00000000)
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#define NV_DPCD_REV_MAJOR_SHIFT (4)
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#define NV_DPCD_REV_MAJOR_MASK (0xf << 4)
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#define NV_DPCD_REV_MINOR_SHIFT (0)
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#define NV_DPCD_REV_MINOR_MASK (0xf)
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#define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GBPS (0x00000006)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GBPS (0x0000000a)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GBPS (0x00000014)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_8_10_GBPS (0x0000001e)
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#define NV_DPCD_MAX_LANE_COUNT (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_MASK (0x1f)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004)
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#define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001 << 6)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7)
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#define NV_DPCD_MAX_DOWNSPREAD (0x00000003)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F (0x00000000 << 6)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (0x00000001 << 6)
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#define NV_DPCD_MAX_DOWNSPREAD_TPS4_SUPPORTED_YES (0x00000001 << 7)
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#define NV_DPCD_EDP_CONFIG_CAP (0x0000000D)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO (0x00000000)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1)
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#define NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES (0x00000001 << 3)
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#define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E)
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#define NV_DPCD_TRAINING_AUX_RD_INTERVAL_MASK (0x3f)
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#define NV_DPCD_EXT_RECEIVER_CAP_FIELD_PRESENT_SHIFT (6)
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#define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100)
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#define NV_DPCD_LANE_COUNT_SET (0x00000101)
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#define NV_DPCD_LANE_COUNT_SET_MASK (0x1f)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T (0x00000001 << 7)
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#define NV_DPCD_TRAINING_PATTERN_SET (0x00000102)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK 0x3
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP4 (0x00000007)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
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#define NV_DPCD_TRAINING_LANE0_SET (0x00000103)
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#define NV_DPCD_TRAINING_LANE1_SET (0x00000104)
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#define NV_DPCD_TRAINING_LANE2_SET (0x00000105)
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#define NV_DPCD_TRAINING_LANE3_SET (0x00000106)
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#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0
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#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
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#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
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#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
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#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
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#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107)
|
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4)
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1
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#define NV_DPCD_EDP_CONFIG_SET (0x0000010A)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE (0x00000000)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE (0x00000001)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001 << 1)
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||
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#define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F)
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#define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110)
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#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0
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#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0x00000000 << 2)
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6)
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0x00000000 << 6)
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#define NV_DPCD_SINK_COUNT (0x00000200)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201)
|
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1)
|
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1)
|
||
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000 << 2)
|
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001 << 2)
|
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#define NV_DPCD_LANE0_1_STATUS (0x00000202)
|
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#define NV_DPCD_LANE2_3_STATUS (0x00000203)
|
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#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
|
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#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
|
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#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
|
||
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
|
||
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
|
||
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
|
||
|
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
|
||
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
|
||
|
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
|
||
|
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
|
||
|
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
|
||
|
|
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
|
||
|
|
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
|
||
|
|
#define NV_DPCD_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE_NO (0x00000000)
|
||
|
|
#define NV_DPCD_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE_YES (0x00000001)
|
||
|
|
#define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206)
|
||
|
|
#define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207)
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2)
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4)
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6
|
||
|
|
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6)
|
||
|
|
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C)
|
||
|
|
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3
|
||
|
|
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2)
|
||
|
|
#define NV_DPCD_TEST_REQUEST (0x00000218)
|
||
|
|
#define NV_DPCD_TEST_REQUEST_TEST_LT (1 << 0)
|
||
|
|
#define NV_DPCD_TEST_REQUEST_TEST_PATTERN (1 << 1)
|
||
|
|
#define NV_DPCD_TEST_REQUEST_TEST_EDID_READ (1 << 2)
|
||
|
|
#define NV_DPCD_TEST_RESPONSE (0x00000260)
|
||
|
|
#define NV_DPCD_TEST_RESPONSE_ACK (1 << 0)
|
||
|
|
#define NV_DPCD_TEST_RESPONSE_NACK (1 << 1)
|
||
|
|
#define NV_DPCD_TEST_EDID_CHECKSUM_WR (1 << 2)
|
||
|
|
#define NV_DPCD_TEST_EDID_CHECKSUM (0x00000261)
|
||
|
|
#define NV_DPCD_SOURCE_IEEE_OUI (0x00000300)
|
||
|
|
#define NV_IEEE_OUI (0x00044b)
|
||
|
|
#define NV_DPCD_SINK_IEEE_OUI (0x00000400)
|
||
|
|
#define NV_DPCD_BRANCH_IEEE_OUI (0x00000500)
|
||
|
|
#define NV_DPCD_SET_POWER (0x00000600)
|
||
|
|
#define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000)
|
||
|
|
#define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001)
|
||
|
|
#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002)
|
||
|
|
#define NV_DPCD_REV_EXT_CAP (0x00002200)
|
||
|
|
#define NV_DPCD_MAX_LINK_BANDWIDTH_EXT_CAP (0x00002201)
|
||
|
|
#define NV_DPCD_FEATURE_ENUM_LIST (0x00002210)
|
||
|
|
#define NV_DPCD_FEATURE_ENUM_LIST_VSC_EXT_COLORIMETRY (1 << 3)
|
||
|
|
#define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000)
|
||
|
|
#define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005)
|
||
|
|
#define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007)
|
||
|
|
#define NV_DPCD_HDCP_AN_OFFSET (0x0006800C)
|
||
|
|
#define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014)
|
||
|
|
#define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028)
|
||
|
|
#define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029)
|
||
|
|
#define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A)
|
||
|
|
#define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C)
|
||
|
|
#define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B)
|
||
|
|
#define NV_DPCP_HDCP_SHA_H0_OFFSET (0x00068014)
|
||
|
|
#define NV_DPCP_HDCP_SHA_H1_OFFSET (0x00068018)
|
||
|
|
#define NV_DPCP_HDCP_SHA_H2_OFFSET (0x0006801C)
|
||
|
|
#define NV_DPCP_HDCP_SHA_H3_OFFSET (0x00068020)
|
||
|
|
#define NV_DPCP_HDCP_SHA_H4_OFFSET (0x00068024)
|
||
|
|
/* DP 2.2 specific registers */
|
||
|
|
#define NV_DPCD_HDCP_RTX_OFFSET (0x00069000)
|
||
|
|
#define NV_DPCD_HDCP_TXCAPS_OFFSET (0x00069008)
|
||
|
|
#define NV_DPCD_HDCP_CERT_RX_OFFSET (0x0006900B)
|
||
|
|
#define NV_DPCD_HDCP_CERT_RRX_OFFSET (0x00069215)
|
||
|
|
#define NV_DPCD_HDCP_CERT_RXCAPS_OFFSET (0x0006921D)
|
||
|
|
#define NV_DPCD_HDCP_EKM_NOSTORED (0x69220)
|
||
|
|
#define NV_DPCD_HDCP_EKM_STORED (0x692A0)
|
||
|
|
#define NV_DPCD_HDCP_M (0x692B0)
|
||
|
|
#define NV_DPCD_HDCP_HPRIME (0x000692C0)
|
||
|
|
#define NV_DPCD_HDCP_EKM_PAIRING (0x0000692E0)
|
||
|
|
#define NV_DPCD_HDCP_RN (0x000692F0)
|
||
|
|
#define NV_DPCD_HDCP_LPRIME (0x000692F8)
|
||
|
|
#define NV_DPCD_HDCP_EKS (0x00069318)
|
||
|
|
#define NV_DPCD_HDCP_RIV (0x00069328)
|
||
|
|
#define NV_DPCD_HDCP_RXINFO (0x00069330)
|
||
|
|
#define NV_DPCD_HDCP_SEQNUM_V (0x00069332)
|
||
|
|
#define NV_DPCD_HDCP_VPRIME (0x00069335)
|
||
|
|
#define NV_DPCD_HDCP_RX_ID_LIST (0x00069345)
|
||
|
|
#define NV_DPCD_HDCP_V (0x000693E0)
|
||
|
|
#define NV_DPCD_HDCP_SEQ_NUM_M (0x000693F0)
|
||
|
|
#define NV_DPCD_HDCP_K (0x000693F3)
|
||
|
|
#define NV_DPCD_HDCP_STRMID_TYPE (0x000693F5)
|
||
|
|
#define NV_DPCD_HDCP_MPRIME (0x00069473)
|
||
|
|
#define NV_DPCD_HDCP_RXSTATUS (0x00069493)
|
||
|
|
#define NV_DPCD_HDCP_RSVD (0x00069494)
|
||
|
|
#define NV_DPCD_HDCP_DBG (0x00069518)
|
||
|
|
|
||
|
|
void tegra_dp_set_max_link_bw(struct tegra_dc_sor_data *sor,
|
||
|
|
struct tegra_dc_dp_link_config *cfg);
|
||
|
|
int tegra_dc_dp_get_max_link_bw(struct tegra_dc_dp_data *dp);
|
||
|
|
int tegra_dc_dp_get_max_lane_count(struct tegra_dc_dp_data *dp, u8 *dpcd_data);
|
||
|
|
int tegra_dp_set_enhanced_framing(struct tegra_dc_dp_data *dp, bool enable);
|
||
|
|
#endif
|