425 lines
17 KiB
C
425 lines
17 KiB
C
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/*
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* hdmi_reg.h: hdmi registers.
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*
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* Copyright (C) 2010 Google, Inc.
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* Author: Erik Gilling <konkers@android.com>
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*
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* Copyright (c) 2010-2017, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_HDMI_REG_H
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#define __DRIVERS_VIDEO_TEGRA_DC_HDMI_REG_H
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#define HDMI_CTXSW 0x00
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#define HDMI_NV_PDISP_SOR_STATE0 0x01
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#define SOR_STATE_UPDATE (1 << 0)
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#define HDMI_NV_PDISP_SOR_STATE1 0x02
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#define SOR_STATE_ASY_HEAD_OPMODE_SLEEP (0 << 0)
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#define SOR_STATE_ASY_HEAD_OPMODE_SNOOSE (1 << 0)
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#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
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#define SOR_STATE_ASY_ORMODE_SAFE (0 << 2)
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#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
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#define SOR_STATE_ATTACHED (1 << 3)
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#define SOR_STATE_ARM_SHOW_VGA (1 << 4)
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#define HDMI_NV_PDISP_SOR_STATE2 0x03
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#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
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#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
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#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
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#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
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#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
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#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
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#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
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#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
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#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
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#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
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#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
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#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
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#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
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#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
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#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
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#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
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#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
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#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
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#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
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#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
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#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
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#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
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#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
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#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
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#define REPEATER (1 << 31)
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#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
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#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
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#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
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#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
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#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
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#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
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#define HDCP_RUN_YES (1 << 0)
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#define CRYPT_ENABLED (1 << 1)
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#define ONEONE_ENABLED (1 << 3)
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#define AN_VALID (1 << 8)
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#define R0_VALID (1 << 9)
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#define SPRIME_VALID (1 << 10)
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#define MPRIME_VALID (1 << 11)
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#define SROM_ERR (1 << 13)
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#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
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#define TMDS0_LINK0 (1 << 4)
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#define READ_S (1 << 0)
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#define READ_M (2 << 0)
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#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
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#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
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#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
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#define STATUS_CS (1 << 6)
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#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
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#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
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#define HDMI_NV_PDISP_RG_HDCP_RI 0x17
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#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
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#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
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#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
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#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
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#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
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#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
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#define INFOFRAME_CTRL_ENABLE (1 << 0)
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#define INFOFRAME_CTRL_OTHER (1 << 4)
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#define INFOFRAME_CTRL_SINGLE (1 << 8)
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#define INFOFRAME_HEADER_TYPE(x) ((x) & 0xff)
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#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
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#define INFOFRAME_HEADER_LEN(x) (((x) & 0xf) << 16)
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#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
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#define GENERIC_CTRL_ENABLE (1 << 0)
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#define GENERIC_CTRL_OTHER (1 << 4)
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#define GENERIC_CTRL_SINGLE (1 << 8)
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#define GENERIC_CTRL_HBLANK (1 << 12)
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#define GENERIC_CTRL_AUDIO (1 << 16)
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#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
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#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
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#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
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#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
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#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
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#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
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#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
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#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
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#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
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#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
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#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
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#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
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#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
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#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
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#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
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#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
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#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
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#define ACR_SB3(x) (((x) & 0xff) << 8)
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#define ACR_SB2(x) (((x) & 0xff) << 16)
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#define ACR_SB1(x) (((x) & 0xff) << 24)
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#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
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#define ACR_SB6(x) (((x) & 0xff) << 0)
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#define ACR_SB5(x) (((x) & 0xff) << 8)
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#define ACR_SB4(x) (((x) & 0xff) << 16)
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#define ACR_ENABLE (1 << 31)
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#define ACR_SUBPACK_N(x) ((x) & 0xffffff)
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#define HDMI_NV_PDISP_HDMI_CTRL 0x44
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#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
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#define HDMI_CTRL_AUDIO_LAYOUT (1 << 8)
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#define HDMI_CTRL_SAMPLE_FLAT (1 << 12)
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#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
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#define HDMI_CTRL_ENABLE (1 << 30)
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#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
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#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
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#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
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#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
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#define VSYNC_WINDOW_ENABLE (1 << 31)
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#define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
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#define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
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#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
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#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
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#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
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#define HDMI_NV_PDISP_HDMI_EMU0 0x4c
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#define HDMI_NV_PDISP_HDMI_EMU1 0x4d
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#define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
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#define HDMI_NV_PDISP_HDMI_SPARE 0x4f
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#define SPARE_HW_CTS (1 << 0)
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#define SPARE_FORCE_SW_CTS (1 << 1)
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#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
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#define SPARE_ACR_PRIORITY_HIGH (0 << 31)
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#define SPARE_ACR_PRIORITY_LOW (1 << 31)
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#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
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#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
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#define HDMI_NV_PDISP_HDCPRIF_ROM_CTRL 0x53
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#define HDMI_NV_PDISP_SOR_CAP 0x54
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#define HDMI_NV_PDISP_SOR_PWR 0x55
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#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
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#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
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#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
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#define SOR_PWR_NORMAL_START_ALT (1 << 1)
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#define SOR_PWR_SAFE_STATE_PD (0 << 16)
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#define SOR_PWR_SAFE_STATE_PU (1 << 16)
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#define SOR_PWR_SAFE_START_NORMAL (0 << 17)
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#define SOR_PWR_SAFE_START_ALT (1 << 17)
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#define SOR_PWR_HALT_DELAY (1 << 24)
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#define SOR_PWR_MODE (1 << 28)
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#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
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#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
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#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
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#define HDMI_NV_PDISP_SOR_TEST 0x56
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#define HDMI_NV_PDISP_SOR_PLL0 0x57
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#define SOR_PLL_PWR_OFF (1 << 0)
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#define SOR_PLL_RESISTORSEL_EXT (1 << 4)
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#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
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#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
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#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
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#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
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#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0x3) << 28)
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#define HDMI_NV_PDISP_SOR_PLL1 0x58
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#define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
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#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
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#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
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#define SOR_PLL_PE_EN (1 << 28)
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#define SOR_PLL_HALF_FULL_PE (1 << 29)
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#define SOR_PLL_S_D_PIN_PE (1 << 30)
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#define HDMI_NV_PDISP_SOR_PLL2 0x59
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#define HDMI_NV_PDISP_SOR_CSTM 0x5a
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#define SOR_CSTM_PD_TXDA_0 (1 << 0)
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#define SOR_CSTM_PD_TXDA_1 (1 << 1)
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#define SOR_CSTM_PD_TXDA_2 (1 << 2)
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#define SOR_CSTM_PD_TXDA_3 (1 << 3)
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#define SOR_CSTM_PD_TXDB_0 (1 << 4)
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#define SOR_CSTM_PD_TXDB_1 (1 << 5)
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#define SOR_CSTM_PD_TXDB_2 (1 << 6)
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#define SOR_CSTM_PD_TXDB_3 (1 << 7)
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#define SOR_CSTM_PD_TXCA (1 << 8)
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#define SOR_CSTM_PD_TXCB (1 << 9)
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#define SOR_CSTM_UPPER (1 << 11)
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#define SOR_CSTM_MODE(x) (((x) & 0x3) << 12)
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#define SOR_CSTM_LINKACTA (1 << 14)
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#define SOR_CSTM_LINKACTB (1 << 15)
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#define SOR_CSTM_LVDS_EN (1 << 16)
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#define SOR_CSTM_DUP_SYNC (1 << 17)
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#define SOR_CSTM_NEW_MODE (1 << 18)
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#define SOR_CSTM_BALANCED (1 << 19)
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#define SOR_CSTM_PLLDIV (1 << 21)
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#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
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#define SOR_CSTM_ROTDAT(x) (((x) & 0x7) << 28)
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#define HDMI_NV_PDISP_SOR_LVDS 0x5b
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#define HDMI_NV_PDISP_SOR_CRCA 0x5c
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#define HDMI_NV_PDISP_SOR_CRCB 0x5d
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#define HDMI_NV_PDISP_SOR_BLANK 0x5e
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#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
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#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
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#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
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#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
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#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
|
||
|
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#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
|
||
|
|
#define SOR_SEQ_STATUS (1 << 28)
|
||
|
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#define SOR_SEQ_SWITCH (1 << 30)
|
||
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|
||
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#define HDMI_NV_PDISP_SOR_SEQ_INST0 0x60
|
||
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#define HDMI_NV_PDISP_SOR_SEQ_INST1 0x61
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST2 0x62
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST3 0x63
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST4 0x64
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST5 0x65
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST6 0x66
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST7 0x67
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INST8 0x68
|
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|
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#define HDMI_NV_PDISP_SOR_SEQ_INST9 0x69
|
||
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#define HDMI_NV_PDISP_SOR_SEQ_INSTA 0x6a
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INSTB 0x6b
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INSTC 0x6c
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INSTD 0x6d
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INSTE 0x6e
|
||
|
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#define HDMI_NV_PDISP_SOR_SEQ_INSTF 0x6f
|
||
|
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#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
|
||
|
|
#define SOR_SEQ_INST_WAIT_UNITS_US (0 << 12)
|
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|
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#define SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12)
|
||
|
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#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
|
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|
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#define SOR_SEQ_INST_HALT (1 << 15)
|
||
|
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#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
|
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|
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#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
|
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|
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#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
|
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|
|
#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
|
||
|
|
#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
|
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|
|
#define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
|
||
|
|
#define SOR_SEQ_INST_SOR_SEQ_INST_BLACK_DATA (1 << 25)
|
||
|
|
#define SOR_SEQ_INST_BLANK_DE (1 << 26)
|
||
|
|
#define SOR_SEQ_INST_BLANK_H (1 << 27)
|
||
|
|
#define SOR_SEQ_INST_BLANK_V (1 << 28)
|
||
|
|
#define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29)
|
||
|
|
#define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
|
||
|
|
#define SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_SOR_VCRCA0 0x72
|
||
|
|
#define HDMI_NV_PDISP_SOR_VCRCA1 0x73
|
||
|
|
#define HDMI_NV_PDISP_SOR_CCRCA0 0x74
|
||
|
|
#define HDMI_NV_PDISP_SOR_CCRCA1 0x75
|
||
|
|
#define HDMI_NV_PDISP_SOR_EDATAA0 0x76
|
||
|
|
#define HDMI_NV_PDISP_SOR_EDATAA1 0x77
|
||
|
|
#define HDMI_NV_PDISP_SOR_COUNTA0 0x78
|
||
|
|
#define HDMI_NV_PDISP_SOR_COUNTA1 0x79
|
||
|
|
#define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
|
||
|
|
#define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
|
||
|
|
#define HDMI_NV_PDISP_SOR_TRIG 0x7c
|
||
|
|
#define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
|
||
|
|
#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
|
||
|
|
/* 31:24 - DRIVE_CURRENT_LANE3
|
||
|
|
* 23:16 - DRIVE_CURRENT_LANE2
|
||
|
|
* 15:8 - DRIVE_CURRENT_LANE1
|
||
|
|
* 7:0 - DRIVE_CURRENT_LANE0
|
||
|
|
*/
|
||
|
|
#define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
|
||
|
|
|
||
|
|
/* note: datasheet defines FS1..FS7. we have FS(0)..FS(6) */
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
|
||
|
|
#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
|
||
|
|
#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0 0xac
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0 0xae
|
||
|
|
#define HDMI_AUDIO_HBR_ENABLE_SHIFT 27
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0 0xbc
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0 0xbd
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0 0xbf
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0 0xc0
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0 0xc1
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0 0xc2
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0 0xc3
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0 0xc4
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0 0xc5
|
||
|
|
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0 0xc6
|
||
|
|
#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
|
||
|
|
#define AUDIO_CNTRL0_SOFT_RESET (1 << 8)
|
||
|
|
#define AUDIO_CNTRL0_SOFT_RESET_ALL (1 << 12)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_UNKNOWN (1 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_32K (2 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_44_1K (0 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_48K (2 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_88_2K (8 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_96K (10 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_176_4K (12 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SAMPLING_FREQ_192K (14 << 16)
|
||
|
|
#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
|
||
|
|
#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
|
||
|
|
#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
|
||
|
|
#define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
|
||
|
|
#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_AUDIO_N 0x8c
|
||
|
|
#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
|
||
|
|
#define AUDIO_N_RESETF (1 << 20)
|
||
|
|
#define AUDIO_N_GENERATE_NORMAL (0 << 24)
|
||
|
|
#define AUDIO_N_GENERATE_ALTERNALTE (1 << 24)
|
||
|
|
#define AUDIO_N_LOOKUP_ENABLE (1 << 28)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
|
||
|
|
#define HDMI_NV_PDISP_SOR_REFCLK 0x95
|
||
|
|
#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
|
||
|
|
#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_CRC_CONTROL 0x96
|
||
|
|
#define HDMI_NV_PDISP_INPUT_CONTROL 0x97
|
||
|
|
#define HDMI_SRC_DISPLAYA (0 << 0)
|
||
|
|
#define HDMI_SRC_DISPLAYB (1 << 0)
|
||
|
|
#define ARM_VIDEO_RANGE_FULL (0 << 1)
|
||
|
|
#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_SCRATCH 0x98
|
||
|
|
#define HDMI_NV_PDISP_PE_CURRENT 0x99
|
||
|
|
/* 27:24 - PE_CURRENT3
|
||
|
|
* 19:16 - PE_CURRENT2
|
||
|
|
* 11:8 - PE_CURRENT1
|
||
|
|
* 3:0 - PE_CURRENT0
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_KEY_CTRL 0x9a
|
||
|
|
#define LOCAL_KEYS (1 << 0)
|
||
|
|
#define AUTOINC (1 << 1)
|
||
|
|
#define WRITE16 (1 << 4)
|
||
|
|
#define PKEY_REQUEST_RELOAD_TRIGGER (1 << 5)
|
||
|
|
#define PKEY_LOADED (1 << 6)
|
||
|
|
#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
|
||
|
|
#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
|
||
|
|
#define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
|
||
|
|
#define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
|
||
|
|
#define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
|
||
|
|
#define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
|
||
|
|
#define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
|
||
|
|
#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
|
||
|
|
#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
|
||
|
|
|
||
|
|
/* registers for ARCH_TEGRA_11x_SOC and later */
|
||
|
|
#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
|
||
|
|
/* 31:24 - PEAK_CURRENT_LANE3
|
||
|
|
* 23:16 - PEAK_CURRENT_LANE2
|
||
|
|
* 15:8 - PEAK_CURRENT_LANE1
|
||
|
|
* 7:0 - PEAK_CURRENT_LANE0
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2
|
||
|
|
#define DRIVE_CURRENT_FUSE_OVERRIDE_T11x (1 << 31)
|
||
|
|
#define HDMI_NV_PDISP_SOR_PAD_CTLS1 0xd3
|
||
|
|
|
||
|
|
/* registers for ARCH_TEGRA_12x_SOC and later */
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL 0xd6
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS 0xd7
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER 0xd8
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW 0xd9
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH 0xda
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW 0xdb
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH 0xdc
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW 0xdd
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH 0xde
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW 0xdf
|
||
|
|
#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH 0xe0
|
||
|
|
|
||
|
|
#endif
|