596 lines
16 KiB
C
596 lines
16 KiB
C
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/*
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* drivers/video/tegra/dc/nvdisp/nvdisp_crc.c
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*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <uapi/video/tegra_dc_ext.h>
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#include "dc_priv.h"
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#include "dc_priv_defs.h"
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#include "hw_nvdisp_nvdisp.h"
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#include "nvdisp_priv.h"
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static struct tegra_nvdisp_rg_region_regs {
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u32 point;
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u32 size;
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u32 golden_crc;
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} regs[TEGRA_DC_EXT_MAX_REGIONS];
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/* Masks for different functional bits across control/status registers */
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static struct tegra_nvdisp_rg_region_masks {
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u32 pending;
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u32 error;
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u32 enable;
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} masks[TEGRA_DC_EXT_MAX_REGIONS];
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/* Unlike G++, GCC does not allow using static inlines as member initializers
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* of static variables.
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*/
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void tegra_nvdisp_crc_region_init(void)
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{
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regs[0].point = nvdisp_rg_region_0_point_r();
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regs[0].size = nvdisp_rg_region_0_size_r();
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regs[0].golden_crc = nvdisp_rg_region_0_golden_crc_r();
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regs[1].point = nvdisp_rg_region_1_point_r();
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regs[1].size = nvdisp_rg_region_1_size_r();
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regs[1].golden_crc = nvdisp_rg_region_1_golden_crc_r();
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regs[2].point = nvdisp_rg_region_2_point_r();
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regs[2].size = nvdisp_rg_region_2_size_r();
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regs[2].golden_crc = nvdisp_rg_region_2_golden_crc_r();
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regs[3].point = nvdisp_rg_region_3_point_r();
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regs[3].size = nvdisp_rg_region_3_size_r();
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regs[3].golden_crc = nvdisp_rg_region_3_golden_crc_r();
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regs[4].point = nvdisp_rg_region_4_point_r();
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regs[4].size = nvdisp_rg_region_4_size_r();
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regs[4].golden_crc = nvdisp_rg_region_4_golden_crc_r();
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regs[5].point = nvdisp_rg_region_5_point_r();
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regs[5].size = nvdisp_rg_region_5_size_r();
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regs[5].golden_crc = nvdisp_rg_region_5_golden_crc_r();
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regs[6].point = nvdisp_rg_region_6_point_r();
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regs[6].size = nvdisp_rg_region_6_size_r();
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regs[6].golden_crc = nvdisp_rg_region_6_golden_crc_r();
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regs[7].point = nvdisp_rg_region_7_point_r();
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regs[7].size = nvdisp_rg_region_7_size_r();
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regs[7].golden_crc = nvdisp_rg_region_7_golden_crc_r();
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regs[8].point = nvdisp_rg_region_8_point_r();
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regs[8].size = nvdisp_rg_region_8_size_r();
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regs[8].golden_crc = nvdisp_rg_region_8_golden_crc_r();
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masks[0].pending = nvdisp_rg_region_crc_region0_pending_yes_f();
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masks[0].error = nvdisp_rg_region_crc_region0_error_yes_f();
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masks[0].enable = nvdisp_rg_region_crc_control_region0_enable_f();
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masks[1].pending = nvdisp_rg_region_crc_region1_pending_yes_f();
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masks[1].error = nvdisp_rg_region_crc_region1_error_yes_f();
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masks[1].enable = nvdisp_rg_region_crc_control_region1_enable_f();
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masks[2].pending = nvdisp_rg_region_crc_region2_pending_yes_f();
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masks[2].error = nvdisp_rg_region_crc_region2_error_yes_f();
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masks[2].enable = nvdisp_rg_region_crc_control_region2_enable_f();
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masks[3].pending = nvdisp_rg_region_crc_region3_pending_yes_f();
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masks[3].error = nvdisp_rg_region_crc_region3_error_yes_f();
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masks[3].enable = nvdisp_rg_region_crc_control_region3_enable_f();
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masks[4].pending = nvdisp_rg_region_crc_region4_pending_yes_f();
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masks[4].error = nvdisp_rg_region_crc_region4_error_yes_f();
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masks[4].enable = nvdisp_rg_region_crc_control_region4_enable_f();
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masks[5].pending = nvdisp_rg_region_crc_region5_pending_yes_f();
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masks[5].error = nvdisp_rg_region_crc_region5_error_yes_f();
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masks[5].enable = nvdisp_rg_region_crc_control_region5_enable_f();
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masks[6].pending = nvdisp_rg_region_crc_region6_pending_yes_f();
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masks[6].error = nvdisp_rg_region_crc_region6_error_yes_f();
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masks[6].enable = nvdisp_rg_region_crc_control_region6_enable_f();
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masks[7].pending = nvdisp_rg_region_crc_region7_pending_yes_f();
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masks[7].error = nvdisp_rg_region_crc_region7_error_yes_f();
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masks[7].enable = nvdisp_rg_region_crc_control_region7_enable_f();
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masks[8].pending = nvdisp_rg_region_crc_region8_pending_yes_f();
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masks[8].error = nvdisp_rg_region_crc_region8_error_yes_f();
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masks[8].enable = nvdisp_rg_region_crc_control_region8_enable_f();
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}
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static int tegra_nvdisp_crc_region_enable(struct tegra_dc *dc,
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struct tegra_dc_ext_crc_conf *conf)
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{
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struct tegra_dc_ext_crc_region *region = &conf->region;
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u32 point, size, control, status;
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u32 crc_readback_location_mask =
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nvdisp_rg_region_crc_control_readback_location_readback_golden_f();
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if (conf->crc.valid) {
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dev_err(&dc->ndev->dev,
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"Programming golden CRCs is yet to be supported\n");
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return -ENOTSUPP;
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}
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status = tegra_dc_readl(dc, nvdisp_rg_region_crc_r());
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status |= masks[region->id].pending;
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tegra_dc_writel(dc, status, nvdisp_rg_region_crc_r());
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/*
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* HW Bug 2038907: In DP mode, vertical calculations are off by
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* 1 line. Adjust them to match exactly with HDMI mode.
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*/
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if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
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dc->out->type == TEGRA_DC_OUT_DP) {
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if (region->y == 0)
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region->h += 1;
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else
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region->y += 1;
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}
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point = nvdisp_rg_region_0_point_x_f(region->x) |
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nvdisp_rg_region_0_point_y_f(region->y);
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tegra_dc_writel(dc, point, regs[region->id].point);
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size = nvdisp_rg_region_0_size_width_f(region->w) |
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nvdisp_rg_region_0_size_height_f(region->h);
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tegra_dc_writel(dc, size, regs[region->id].size);
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control = tegra_dc_readl(dc, nvdisp_rg_region_crc_control_r());
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control |= masks[region->id].enable;
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/* TODO: This is yet to be supported. We return -ENOTSUPP at the
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* begnning of the function for this case
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*/
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if (conf->crc.valid) {
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control |= crc_readback_location_mask;
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tegra_dc_writel(dc, conf->crc.val,
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regs[region->id].golden_crc);
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}
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tegra_dc_writel(dc, control, nvdisp_rg_region_crc_control_r());
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return 0;
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}
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static void tegra_nvdisp_crc_rg_comp_enable(struct tegra_dc *dc,
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struct tegra_dc_ext_crc_conf *conf)
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{
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u32 ctl = nvdisp_crc_control_enable_enable_f();
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enum tegra_dc_ext_crc_input_data input_data = conf->input_data;
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if (input_data == TEGRA_DC_EXT_CRC_INPUT_DATA_FULL_FRAME)
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ctl |= nvdisp_crc_control_input_data_full_frame_f();
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else
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ctl |= nvdisp_crc_control_input_data_active_data_f();
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tegra_dc_writel(dc, ctl, nvdisp_crc_control_r());
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}
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int tegra_nvdisp_crc_enable(struct tegra_dc *dc,
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struct tegra_dc_ext_crc_conf *conf)
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{
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int ret = 0;
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enum tegra_dc_ext_crc_type type = conf->type;
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u8 id; /* region id */
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mutex_lock(&dc->lock);
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tegra_dc_get(dc);
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switch (type) {
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case TEGRA_DC_EXT_CRC_TYPE_RG_REGIONAL:
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id = conf->region.id;
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if (id >= TEGRA_DC_EXT_MAX_REGIONS) {
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ret = -EINVAL;
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goto error_out;
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}
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ret = tegra_nvdisp_crc_region_enable(dc, conf);
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if (ret)
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goto error_out;
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atomic_inc(&dc->crc_ref_cnt.region[id]);
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atomic_inc(&dc->crc_ref_cnt.regional);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_RG:
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tegra_nvdisp_crc_rg_comp_enable(dc, conf);
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atomic_inc(&dc->crc_ref_cnt.rg);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_COMP:
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tegra_nvdisp_crc_rg_comp_enable(dc, conf);
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atomic_inc(&dc->crc_ref_cnt.comp);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_OR:
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if (!dc->out_ops->crc_en) {
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ret = -ENOTSUPP;
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goto error_out;
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}
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ret = dc->out_ops->crc_en(dc, &conf->or_params);
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if (ret)
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goto error_out;
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atomic_inc(&dc->crc_ref_cnt.out);
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break;
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default:
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ret = -ENOTSUPP;
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goto error_out;
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}
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tegra_dc_put(dc);
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mutex_unlock(&dc->lock);
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if (atomic_inc_return(&dc->crc_ref_cnt.global) == 1) {
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ret = tegra_dc_config_frame_end_intr(dc, true);
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if (ret) {
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atomic_dec(&dc->crc_ref_cnt.global);
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switch (type) {
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case TEGRA_DC_EXT_CRC_TYPE_RG_REGIONAL:
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id = conf->region.id;
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atomic_dec(&dc->crc_ref_cnt.regional);
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atomic_dec(&dc->crc_ref_cnt.region[id]);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_RG:
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atomic_dec(&dc->crc_ref_cnt.rg);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_COMP:
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atomic_dec(&dc->crc_ref_cnt.comp);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_OR:
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atomic_dec(&dc->crc_ref_cnt.out);
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break;
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default:
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return -ENOTSUPP;
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}
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return ret;
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}
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}
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return 0;
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error_out:
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tegra_dc_put(dc);
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mutex_unlock(&dc->lock);
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return ret;
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}
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static void tegra_nvdisp_crc_region_disable(struct tegra_dc *dc,
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struct tegra_dc_ext_crc_conf *conf)
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{
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struct tegra_dc_ext_crc_region *region = &conf->region;
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u32 control;
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tegra_dc_writel(dc, 0x0, regs[region->id].point);
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tegra_dc_writel(dc, 0x0, regs[region->id].size);
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tegra_dc_writel(dc, 0x0, regs[region->id].golden_crc);
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control = tegra_dc_readl(dc, nvdisp_rg_region_crc_control_r());
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control ^= masks[region->id].enable;
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tegra_dc_writel(dc, control, nvdisp_rg_region_crc_control_r());
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}
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int tegra_nvdisp_crc_disable(struct tegra_dc *dc,
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struct tegra_dc_ext_crc_conf *conf)
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{
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int ret = 0;
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enum tegra_dc_ext_crc_type type = conf->type;
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u8 id; /* region id */
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mutex_lock(&dc->lock);
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tegra_dc_get(dc);
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switch (type) {
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case TEGRA_DC_EXT_CRC_TYPE_RG_REGIONAL:
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id = conf->region.id;
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if (id >= TEGRA_DC_EXT_MAX_REGIONS) {
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ret = -EINVAL;
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goto error_out;
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}
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if (!atomic_dec_return(&dc->crc_ref_cnt.region[id]))
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tegra_nvdisp_crc_region_disable(dc, conf);
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atomic_dec(&dc->crc_ref_cnt.regional);
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break;
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case TEGRA_DC_EXT_CRC_TYPE_RG:
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if (atomic_dec_return(&dc->crc_ref_cnt.rg) == 0 &&
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atomic_read(&dc->crc_ref_cnt.comp) == 0)
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tegra_dc_writel(dc, 0x0, nvdisp_crc_control_r());
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break;
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case TEGRA_DC_EXT_CRC_TYPE_COMP:
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if (atomic_dec_return(&dc->crc_ref_cnt.comp) == 0 &&
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atomic_read(&dc->crc_ref_cnt.rg) == 0)
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tegra_dc_writel(dc, 0x0, nvdisp_crc_control_r());
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break;
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case TEGRA_DC_EXT_CRC_TYPE_OR:
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if (atomic_dec_return(&dc->crc_ref_cnt.out) == 0) {
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if (!dc->out_ops->crc_dis) {
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|
|
ret = -ENOTSUPP;
|
||
|
|
goto error_out;
|
||
|
|
}
|
||
|
|
ret = dc->out_ops->crc_dis(dc, &conf->or_params);
|
||
|
|
if (ret) {
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.out);
|
||
|
|
goto error_out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
ret = -ENOTSUPP;
|
||
|
|
goto error_out;
|
||
|
|
}
|
||
|
|
|
||
|
|
tegra_dc_put(dc);
|
||
|
|
mutex_unlock(&dc->lock);
|
||
|
|
|
||
|
|
if (atomic_dec_return(&dc->crc_ref_cnt.global) == 0) {
|
||
|
|
ret = tegra_dc_config_frame_end_intr(dc, false);
|
||
|
|
if (ret) {
|
||
|
|
switch (type) {
|
||
|
|
case TEGRA_DC_EXT_CRC_TYPE_RG_REGIONAL:
|
||
|
|
id = conf->region.id;
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.region[id]);
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.regional);
|
||
|
|
break;
|
||
|
|
case TEGRA_DC_EXT_CRC_TYPE_RG:
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.rg);
|
||
|
|
break;
|
||
|
|
case TEGRA_DC_EXT_CRC_TYPE_COMP:
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.comp);
|
||
|
|
break;
|
||
|
|
case TEGRA_DC_EXT_CRC_TYPE_OR:
|
||
|
|
atomic_inc(&dc->crc_ref_cnt.out);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -ENOTSUPP;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
error_out:
|
||
|
|
tegra_dc_put(dc);
|
||
|
|
mutex_unlock(&dc->lock);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool is_region_enabled(u32 ctl, int id)
|
||
|
|
{
|
||
|
|
return ctl & masks[id].enable;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool is_region_crc_ready(u32 status, int id)
|
||
|
|
{
|
||
|
|
return status & masks[id].pending;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_nvdisp_crc_rg_regional_get(struct tegra_dc *dc,
|
||
|
|
struct tegra_dc_crc_buf_ele *e)
|
||
|
|
{
|
||
|
|
int id, ret = 0;
|
||
|
|
u32 ctl, status;
|
||
|
|
u32 frame_cnt;
|
||
|
|
u32 crc_readback_location_mask =
|
||
|
|
nvdisp_rg_region_crc_control_readback_location_readback_golden_f();
|
||
|
|
|
||
|
|
status = tegra_dc_readl(dc, nvdisp_rg_region_crc_r());
|
||
|
|
|
||
|
|
ctl = tegra_dc_readl(dc, nvdisp_rg_region_crc_control_r());
|
||
|
|
if (ctl & crc_readback_location_mask) {
|
||
|
|
dev_err(&dc->ndev->dev,
|
||
|
|
"Golden CRCs are already programmed. Ignore reading "
|
||
|
|
"status = %#x, ctl = %#x\n", status, ctl);
|
||
|
|
return -EPERM;
|
||
|
|
}
|
||
|
|
|
||
|
|
frame_cnt = tegra_dc_get_frame_cnt(dc);
|
||
|
|
|
||
|
|
for (id = 0; id < TEGRA_DC_MAX_CRC_REGIONS; id++) {
|
||
|
|
if (!is_region_enabled(ctl, id))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (!is_region_crc_ready(status, id)) {
|
||
|
|
trace_display_crc_rgnl_stat(dc->ctrl_num, frame_cnt,
|
||
|
|
"RGN", id, status);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Clearing out the error bit is a functional no-op, since the
|
||
|
|
* error bit simply signifies that the HW calculated CRC value
|
||
|
|
* is different from the value programmed in the golden
|
||
|
|
* register, or lack thereof. However, we clear it to avoid
|
||
|
|
* confusion when reading register dumps
|
||
|
|
*/
|
||
|
|
if (status & masks[id].error)
|
||
|
|
status |= masks[id].error;
|
||
|
|
|
||
|
|
e->regional[id].crc = tegra_dc_readl(dc, regs[id].golden_crc);
|
||
|
|
e->regional[id].valid = true;
|
||
|
|
status |= masks[id].pending;
|
||
|
|
|
||
|
|
trace_display_crc_rgnl(dc->ctrl_num, frame_cnt, "RGN",
|
||
|
|
id, status, e->regional[id].crc);
|
||
|
|
}
|
||
|
|
|
||
|
|
tegra_dc_writel(dc, status, nvdisp_rg_region_crc_r());
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_nvdisp_crc_rg_get(struct tegra_dc *dc,
|
||
|
|
struct tegra_dc_crc_buf_ele *e)
|
||
|
|
{
|
||
|
|
u32 status;
|
||
|
|
u32 frame_cnt;
|
||
|
|
|
||
|
|
status = tegra_dc_readl(dc, nvdisp_rg_crca_r());
|
||
|
|
frame_cnt = tegra_dc_get_frame_cnt(dc);
|
||
|
|
|
||
|
|
if (status & nvdisp_rg_crca_valid_true_f()) {
|
||
|
|
e->rg.crc = tegra_dc_readl(dc, nvdisp_rg_crcb_r());
|
||
|
|
e->rg.valid = true;
|
||
|
|
trace_display_crc_read(dc->ctrl_num, frame_cnt, "RG ",
|
||
|
|
status, e->rg.crc);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & nvdisp_rg_crca_error_true_f()) {
|
||
|
|
trace_display_crc_late(dc->ctrl_num, frame_cnt, "RG ",
|
||
|
|
e->rg.valid, e->rg.crc);
|
||
|
|
if (!e->rg.valid)
|
||
|
|
e->rg.crc = 0;
|
||
|
|
status |= nvdisp_rg_crca_error_true_f();
|
||
|
|
tegra_dc_writel(dc, status, nvdisp_rg_crca_r());
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_nvdisp_crc_comp_get(struct tegra_dc *dc,
|
||
|
|
struct tegra_dc_crc_buf_ele *e)
|
||
|
|
{
|
||
|
|
u32 status;
|
||
|
|
u32 frame_cnt;
|
||
|
|
|
||
|
|
status = tegra_dc_readl(dc, nvdisp_comp_crca_r());
|
||
|
|
frame_cnt = tegra_dc_get_frame_cnt(dc);
|
||
|
|
|
||
|
|
if (status & nvdisp_comp_crca_valid_true_f()) {
|
||
|
|
e->comp.crc = tegra_dc_readl(dc, nvdisp_comp_crcb_r());
|
||
|
|
e->comp.valid = true;
|
||
|
|
trace_display_crc_read(dc->ctrl_num, frame_cnt, "COMP",
|
||
|
|
status, e->comp.crc);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & nvdisp_comp_crca_error_true_f()) {
|
||
|
|
trace_display_crc_late(dc->ctrl_num, frame_cnt, "COMP",
|
||
|
|
e->comp.valid, e->comp.crc);
|
||
|
|
if (!e->comp.valid)
|
||
|
|
e->comp.crc = 0;
|
||
|
|
status |= nvdisp_comp_crca_error_true_f();
|
||
|
|
tegra_dc_writel(dc, status, nvdisp_comp_crca_r());
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_nvdisp_crc_or_get(struct tegra_dc *dc,
|
||
|
|
struct tegra_dc_crc_buf_ele *e)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (dc->out_ops->crc_get) {
|
||
|
|
ret = dc->out_ops->crc_get(dc, &e->sor.crc);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
e->sor.valid = true;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int tegra_nvdisp_crc_collect(struct tegra_dc *dc,
|
||
|
|
struct tegra_dc_crc_buf_ele *e)
|
||
|
|
{
|
||
|
|
#define NEXT_FRAME_POLL_DELAY_US 1
|
||
|
|
#define FRAME_BOUNDARY_CROSSING_RETRIES 5
|
||
|
|
int ret = 0, iter;
|
||
|
|
int max_retries = FRAME_BOUNDARY_CROSSING_RETRIES;
|
||
|
|
bool valids = false; /* Logical OR of valid fields of individual CRCs */
|
||
|
|
u32 frame_cnt_start;
|
||
|
|
u32 frame_cnt_end;
|
||
|
|
|
||
|
|
retry:
|
||
|
|
frame_cnt_start = tegra_dc_get_frame_cnt(dc);
|
||
|
|
|
||
|
|
if (atomic_read(&dc->crc_ref_cnt.rg))
|
||
|
|
tegra_nvdisp_crc_rg_get(dc, e);
|
||
|
|
|
||
|
|
if (atomic_read(&dc->crc_ref_cnt.comp))
|
||
|
|
tegra_nvdisp_crc_comp_get(dc, e);
|
||
|
|
|
||
|
|
if (atomic_read(&dc->crc_ref_cnt.out))
|
||
|
|
tegra_nvdisp_crc_or_get(dc, e);
|
||
|
|
|
||
|
|
if (atomic_read(&dc->crc_ref_cnt.regional))
|
||
|
|
ret = tegra_nvdisp_crc_rg_regional_get(dc, e);
|
||
|
|
|
||
|
|
frame_cnt_end = tegra_dc_get_frame_cnt(dc);
|
||
|
|
|
||
|
|
if (frame_cnt_end != frame_cnt_start) {
|
||
|
|
unsigned long timeout_jf;
|
||
|
|
u32 frame_cnt_retry;
|
||
|
|
|
||
|
|
trace_display_crc_boundary_crossed(dc->ctrl_num,
|
||
|
|
frame_cnt_start, frame_cnt_end,
|
||
|
|
"wait for next frame");
|
||
|
|
|
||
|
|
timeout_jf = jiffies + msecs_to_jiffies(MSEC_PER_SEC << 1);
|
||
|
|
|
||
|
|
do {
|
||
|
|
usleep_range(NEXT_FRAME_POLL_DELAY_US,
|
||
|
|
NEXT_FRAME_POLL_DELAY_US << 1);
|
||
|
|
frame_cnt_retry = tegra_dc_get_frame_cnt(dc);
|
||
|
|
} while ((frame_cnt_end == frame_cnt_retry) &&
|
||
|
|
time_after(timeout_jf, jiffies));
|
||
|
|
|
||
|
|
if (frame_cnt_end == frame_cnt_retry) {
|
||
|
|
dev_err(&dc->ndev->dev,
|
||
|
|
"frame=%u NEXT FRAME POLL TIMEOUT\n",
|
||
|
|
frame_cnt_end);
|
||
|
|
trace_display_crc_boundary_crossed(dc->ctrl_num,
|
||
|
|
frame_cnt_end, frame_cnt_retry,
|
||
|
|
"NEXT FRAME POLL TIMEOUT");
|
||
|
|
return -EBUSY;
|
||
|
|
}
|
||
|
|
if (--max_retries <= 0) {
|
||
|
|
trace_display_crc_boundary_crossed(dc->ctrl_num,
|
||
|
|
frame_cnt_end, frame_cnt_retry,
|
||
|
|
"retries exhausted");
|
||
|
|
return -EBUSY;
|
||
|
|
}
|
||
|
|
trace_display_crc_boundary_crossed(dc->ctrl_num,
|
||
|
|
frame_cnt_end, frame_cnt_retry,
|
||
|
|
"rereading CRCs");
|
||
|
|
goto retry;
|
||
|
|
}
|
||
|
|
|
||
|
|
valids = e->rg.valid || e->comp.valid || e->sor.valid;
|
||
|
|
|
||
|
|
for (iter = 0; iter < TEGRA_DC_EXT_MAX_REGIONS && !valids; iter++)
|
||
|
|
valids = e->regional[iter].valid;
|
||
|
|
|
||
|
|
return valids ? ret : -EINVAL;
|
||
|
|
#undef FRAME_BOUNDARY_CROSSING_RETRIES
|
||
|
|
#undef NEXT_FRAME_POLL_DELAY_US
|
||
|
|
}
|
||
|
|
|
||
|
|
void tegra_nvdisp_crc_reset(struct tegra_dc *dc)
|
||
|
|
{
|
||
|
|
tegra_dc_writel(dc, 0x0, nvdisp_rg_region_crc_control_r());
|
||
|
|
tegra_dc_writel(dc, 0x0, nvdisp_crc_control_r());
|
||
|
|
}
|