444 lines
13 KiB
C
444 lines
13 KiB
C
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/*
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* Copyright (c) 2010-2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _TEGRA_DVFS_H_
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#define _TEGRA_DVFS_H_
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#include <linux/of.h>
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#include <linux/tegra_throttle.h>
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#define MAX_DVFS_FREQS 40
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#define MAX_DVFS_TABLES 80
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#define DVFS_RAIL_STATS_TOP_BIN 100
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#define MAX_THERMAL_LIMITS 8
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#define MAX_THERMAL_RANGES (MAX_THERMAL_LIMITS + 1)
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struct clk;
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struct dvfs_rail;
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/*
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* dvfs_relationship between to rails, "from" and "to"
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* when the rail changes, it will call dvfs_rail_update on the rails
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* in the relationship_to list.
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* when determining the voltage to set a rail to, it will consider each
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* rail in the relationship_from list.
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*/
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struct dvfs_relationship {
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struct dvfs_rail *to;
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struct dvfs_rail *from;
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int (*solve)(struct dvfs_rail *, struct dvfs_rail *);
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struct list_head to_node; /* node in relationship_to list */
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struct list_head from_node; /* node in relationship_from list */
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bool solved_at_nominal;
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bool solved_at_suspend;
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};
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struct rail_stats {
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ktime_t time_at_mv[DVFS_RAIL_STATS_TOP_BIN + 1];
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ktime_t last_update;
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int last_index;
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bool off;
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int bin_uV;
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};
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struct rail_alignment {
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int offset_uv;
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int step_uv; /* Step voltage */
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};
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struct dvfs_rail {
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const char *reg_id;
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int min_millivolts;
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int max_millivolts;
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int reg_max_millivolts;
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int nominal_millivolts; /* Max DVFS voltage */
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int fixed_millivolts;
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int override_millivolts;
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int min_override_millivolts;
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int override_unresolved;
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int (*resolve_override)(int mv);
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const int *therm_mv_floors;
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const int *therm_mv_dfll_floors;
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int therm_mv_floors_num;
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const int *therm_mv_caps;
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int therm_mv_caps_num;
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const int *simon_vmin_offsets;
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int simon_vmin_offs_num;
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int simon_domain;
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int step;
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int step_up;
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bool jmp_to_zero;
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bool in_band_pm;
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bool disabled;
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bool updating;
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bool resolving_to;
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bool rate_set;
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bool dt_reg_fixed;
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bool dt_reg_pwm;
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struct device_node *dt_node; /* device tree rail node */
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struct list_head node; /* node in dvfs_rail_list */
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struct list_head dvfs; /* list head of attached dvfs clocks */
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struct list_head relationships_to;
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struct list_head relationships_from;
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struct regulator *reg;
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int millivolts;
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int new_millivolts;
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int dbg_mv_offs;
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int boot_millivolts;
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int disable_millivolts;
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int suspend_millivolts; /* voltage setting set during suspend */
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bool suspended;
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bool dfll_mode; /* DFLL mode ON/OFF */
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bool dfll_mode_updating;
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int therm_floor_idx; /* index of vmin thermal range */
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int therm_cap_idx; /* index of vmax thermal range */
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int therm_scale_idx; /* index of thermal DVFS or clk source range */
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/* Trips for vmin cooling device */
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struct tegra_cooling_device *vmin_cdev;
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/* Trips for vmax cooling device */
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struct tegra_cooling_device *vmax_cdev;
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/* Trips for thermal DVFS cooling device */
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struct tegra_cooling_device *vts_cdev;
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/* Trips for clock source switch cooling device */
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struct tegra_cooling_device *clk_switch_cdev;
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/* Vmax capping method */
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int (*apply_vmax_cap)(int *cap_idx, int new_idx, int cap_mv);
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struct rail_alignment alignment;
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struct rail_stats stats;
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const char *version;
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};
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/*
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* dfll_range -
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* DFLL_RANGE_NONE : DFLL is not used
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* DFLL_RANGE_ALL_RATES : DFLL is is used for all CPU rates
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* DFLL_RANGE_HIGH_RATES : DFLL is used only for high rates
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* above crossover with PLL dvfs curve
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*/
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enum dfll_range {
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DFLL_RANGE_NONE = 0,
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DFLL_RANGE_ALL_RATES,
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DFLL_RANGE_HIGH_RATES,
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};
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/* DFLL usage is under thermal cooling device control */
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#define TEGRA_USE_DFLL_CDEV_CNTRL 3
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extern int tegra_override_dfll_range;
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/* DVFS settings specific for DFLL clock source */
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struct dvfs_dfll_data {
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u32 tune0;
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u32 tune0_high_mv;
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u32 tune0_simon_mask;
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u32 tune1;
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bool tune0_low_at_cold;
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unsigned long droop_rate_min;
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unsigned long use_dfll_rate_min;
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unsigned long out_rate_min;
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unsigned long max_rate_boost;
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/* Boot frequency if DFLL is enabled by boot-loader; zero otherwise */
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unsigned long dfll_boot_khz;
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int tune_high_min_millivolts;
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int tune_high_margin_mv;
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int min_millivolts;
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enum dfll_range range;
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void (*tune_trimmers)(bool trim_high);
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unsigned int (*is_bypass_down)(void);
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};
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/* DVFS settings specific for PLL clock source */
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struct dvfs_pll_data {
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int min_millivolts;
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};
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struct dvfs {
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const char *clk_name;
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struct clk *clk;
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int speedo_id;
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int process_id;
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/* Must be initialized before tegra_dvfs_init */
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int freqs_mult;
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unsigned long freqs[MAX_DVFS_FREQS];
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const int *millivolts;
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const int *peak_millivolts;
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/* voltage settings as per DFLL clock source */
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const int *dfll_millivolts;
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struct dvfs_rail *dvfs_rail;
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bool auto_dvfs;
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bool can_override;
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bool defer_override;
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bool boost_table;
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/* Filled in by tegra_dvfs_init */
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int max_millivolts;
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int num_freqs;
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struct dvfs_dfll_data dfll_data;
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/* Set if clock rate is adapted by h/w to voltage noise (noise-aware) */
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bool na_dvfs;
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/* Indicates thermal DVFS on/off */
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bool therm_dvfs;
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/* Maximum rate safe at minimum voltage across all thermal ranges */
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unsigned long fmax_at_vmin_safe_t;
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/*
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* Current dvfs point = { index into V/F arrays, voltage, rate request }
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* cur_index is invalid - set to MAX_DVFS_FREQS - if cur_rate and
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* cur_millivolts are set to zero (may happen when dvfs rate is not set
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* initially, or clock is disabled).
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*/
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int cur_index;
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int cur_millivolts;
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unsigned long cur_rate;
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unsigned long *alt_freqs;
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bool use_alt_freqs;
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long dbg_hz_offs;
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struct list_head node;
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struct list_head debug_node;
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struct list_head reg_node;
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struct mutex *lock;
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};
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/* CVB coefficients */
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struct cvb_dvfs_parameters {
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int c0;
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int c1;
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int c2;
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int c3;
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int c4;
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int c5;
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};
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struct cvb_dvfs_table {
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unsigned long freq;
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/* Coeffs for voltage calculation, when dfll clock source is selected */
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struct cvb_dvfs_parameters cvb_dfll_param;
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/* Coeffs for voltage calculation, when pll clock source is selected */
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struct cvb_dvfs_parameters cvb_pll_param;
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};
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struct cvb_dvfs {
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int speedo_id;
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int process_id;
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/* Tuning parameters for dfll */
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struct dvfs_dfll_data dfll_tune_data;
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/* tuning parameters for pll clock */
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struct dvfs_pll_data pll_tune_data;
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/* dvfs Max voltage */
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int max_mv;
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/* dvfs Max frequency */
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unsigned long max_freq;
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int freqs_mult;
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/* scaling values for voltage calculation */
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int speedo_scale;
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int voltage_scale;
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int thermal_scale;
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struct cvb_dvfs_table cvb_vmin;
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/* CVB table for various frequencies */
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struct cvb_dvfs_table cvb_table[MAX_DVFS_FREQS];
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/* Trips for minimal voltage settings per thermal ranges */
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int vmin_trips_table[MAX_THERMAL_LIMITS];
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int therm_floors_table[MAX_THERMAL_LIMITS];
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/* Trips for thermal DVFS per thermal ranges */
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int vts_trips_table[MAX_THERMAL_LIMITS];
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/* Trips for clock source change per thermal ranges */
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int clk_switch_trips[MAX_THERMAL_LIMITS];
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};
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#define cpu_cvb_dvfs cvb_dvfs
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#define gpu_cvb_dvfs cvb_dvfs
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#define core_cvb_dvfs cvb_dvfs
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extern struct dvfs_rail *tegra_cpu_rail;
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extern struct dvfs_rail *tegra_gpu_rail;
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extern struct dvfs_rail *tegra_core_rail;
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struct dvfs_data {
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struct dvfs_rail *rail;
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struct dvfs *tables;
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int *millivolts;
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unsigned int num_tables;
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unsigned int num_voltages;
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};
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#ifdef CONFIG_OF
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typedef int (*of_tegra_dvfs_init_cb_t)(struct device_node *);
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int of_tegra_dvfs_init(const struct of_device_id *matches);
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int of_tegra_dvfs_rail_node_parse(struct device_node *rail_dn,
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struct dvfs_rail *rail);
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int of_tegra_dvfs_rail_get_cdev_trips(
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struct tegra_cooling_device *tegra_cdev, int *therm_trips_table,
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int *therm_limits_table, struct rail_alignment *align, bool up);
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#else
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static inline int of_tegra_dvfs_init(const struct of_device_id *matches)
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{ return -ENODATA; }
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static inline int of_tegra_dvfs_rail_node_parse(struct device_node *rail_dn,
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struct dvfs_rail *rail)
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{ return -ENODEV; }
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static inline int of_tegra_dvfs_rail_get_cdev_trips(
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struct tegra_cooling_device *tegra_cdev, int *therm_trips_table,
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int *therm_limits_table, struct rail_alignment *align, bool up)
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{ return -ENODEV; }
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#endif
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void tegra21x_init_dvfs(void);
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int dvfs_debugfs_init(struct dentry *clk_debugfs_root);
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int tegra_dvfs_rail_connect_regulators(void);
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int tegra_dvfs_rail_register_notifiers(void);
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int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n);
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void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n);
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void tegra_dvfs_rail_enable(struct dvfs_rail *rail);
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void tegra_dvfs_rail_disable(struct dvfs_rail *rail);
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int tegra_dvfs_rail_power_up(struct dvfs_rail *rail);
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int tegra_dvfs_rail_power_down(struct dvfs_rail *rail);
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bool tegra_dvfs_is_rail_up(struct dvfs_rail *rail);
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bool tegra_dvfs_rail_updating(struct clk *clk);
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void tegra_dvfs_rail_off(struct dvfs_rail *rail, ktime_t now);
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void tegra_dvfs_rail_on(struct dvfs_rail *rail, ktime_t now);
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void tegra_dvfs_rail_pause(struct dvfs_rail *rail, ktime_t delta, bool on);
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int tegra_dvfs_rail_set_mode(struct dvfs_rail *rail, unsigned int mode);
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int tegra_dvfs_rail_register_notifier(struct dvfs_rail *rail,
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struct notifier_block *nb);
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int tegra_dvfs_rail_unregister_notifier(struct dvfs_rail *rail,
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struct notifier_block *nb);
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struct dvfs_rail *tegra_dvfs_get_rail_by_name(const char *reg_id);
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int tegra_dvfs_rail_get_current_millivolts(struct dvfs_rail *rail);
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int tegra_dvfs_override_core_cap_apply(int level);
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int tegra_dvfs_therm_vmax_core_cap_apply(int *cap_idx, int new_idx, int level);
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int tegra_dvfs_alt_freqs_install(struct dvfs *d, unsigned long *alt_freqs);
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void tegra_dvfs_alt_freqs_install_always(
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struct dvfs *d, unsigned long *alt_freqs);
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int tegra_dvfs_replace_voltage_table(struct dvfs *d, const int *new_millivolts);
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int tegra_dvfs_butterfly_throttle(struct clk *c1, unsigned long *rate1,
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struct clk *c2, unsigned long *rate2);
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int tegra_dvfs_dfll_mode_set(struct dvfs *d, unsigned long rate);
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int tegra_dvfs_dfll_mode_clear(struct dvfs *d, unsigned long rate);
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int tegra_clk_dfll_range_control(enum dfll_range use_dfll);
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bool tegra_dvfs_is_dfll_scale(struct dvfs *d, unsigned long rate);
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bool tegra_dvfs_is_dfll_range(struct dvfs *d, unsigned long rate);
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int tegra_dvfs_swap_dfll_range(struct dvfs *d, int range, int *old_range);
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int tegra_dvfs_set_dfll_range(struct dvfs *d, int range);
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int tegra_dvfs_rail_set_reg_volatile(struct dvfs_rail *rail, bool set);
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void tegra_clip_freqs(u32 *freqs, int *num_freqs, int freqs_mult,
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const unsigned long *rates_ladder, int num_rates, bool up);
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struct tegra_cooling_device *tegra_dvfs_get_cpu_vmax_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_cpu_vmin_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_core_vmax_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_core_vmin_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_gpu_vmin_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_gpu_vts_cdev(void);
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struct tegra_cooling_device *tegra_dvfs_get_cpu_clk_switch_cdev(void);
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void tegra_dvfs_rail_init_vmin_thermal_profile(
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int *therm_trips_table, int *therm_floors_table,
|
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struct dvfs_rail *rail, struct dvfs_dfll_data *d);
|
||
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void tegra_dvfs_rail_init_vmax_thermal_profile(
|
||
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int *therm_trips_table, int *therm_caps_table,
|
||
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struct dvfs_rail *rail, struct dvfs_dfll_data *d);
|
||
|
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int tegra_dvfs_rail_of_init_vmin_thermal_profile(
|
||
|
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int *therm_trips_table, int *therm_floors_table,
|
||
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struct dvfs_rail *rail, struct dvfs_dfll_data *d);
|
||
|
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int tegra_dvfs_rail_of_init_vmax_thermal_profile(
|
||
|
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int *therm_trips_table, int *therm_caps_table,
|
||
|
|
struct dvfs_rail *rail, struct dvfs_dfll_data *d);
|
||
|
|
int tegra_dvfs_rail_init_clk_switch_thermal_profile(
|
||
|
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int *clk_switch_trips, struct dvfs_rail *rail);
|
||
|
|
int tegra_dvfs_rail_init_thermal_dvfs_trips(
|
||
|
|
int *therm_trips_table, struct dvfs_rail *rail);
|
||
|
|
int tegra_dvfs_init_thermal_dvfs_voltages(int *millivolts,
|
||
|
|
int *peak_millivolts, int freqs_num, int ranges_num, struct dvfs *d);
|
||
|
|
int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail,
|
||
|
|
struct clk *dfll_clk);
|
||
|
|
int tegra_dvfs_rail_get_thermal_floor(struct dvfs_rail *rail);
|
||
|
|
void tegra_dvfs_rail_register_vmax_cdev(struct dvfs_rail *rail);
|
||
|
|
|
||
|
|
#ifdef CONFIG_TEGRA_VDD_CORE_OVERRIDE
|
||
|
|
int tegra_dvfs_resolve_override(struct clk *c, unsigned long max_rate);
|
||
|
|
int tegra_dvfs_rail_get_override_floor(struct dvfs_rail *rail);
|
||
|
|
#else
|
||
|
|
static inline int tegra_dvfs_resolve_override(struct clk *c, unsigned long rate)
|
||
|
|
{ return 0; }
|
||
|
|
static inline int tegra_dvfs_rail_get_override_floor(struct dvfs_rail *rail)
|
||
|
|
{ return 0; }
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static inline int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail)
|
||
|
|
{ return 0; }
|
||
|
|
static inline int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
|
||
|
|
{ return 0; }
|
||
|
|
|
||
|
|
bool tegra_dvfs_is_dfll_bypass(void);
|
||
|
|
|
||
|
|
static inline bool tegra_dvfs_rail_is_dfll_mode(struct dvfs_rail *rail)
|
||
|
|
{
|
||
|
|
return rail ? rail->dfll_mode : false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void tegra_dvfs_rail_mode_updating(struct dvfs_rail *rail,
|
||
|
|
bool updating)
|
||
|
|
{
|
||
|
|
if (rail)
|
||
|
|
rail->dfll_mode_updating = updating;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void tegra_dvfs_set_dfll_tune_trimmers(
|
||
|
|
struct dvfs *d, void (*tune_trimmers)(bool trim_high))
|
||
|
|
{
|
||
|
|
if (d->dfll_data.tune_high_min_millivolts)
|
||
|
|
d->dfll_data.tune_trimmers = tune_trimmers;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|