56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
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/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA CORPORATION and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA CORPORATION is strictly prohibited.
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*/
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#ifndef INCLUDE_CAMRTC_COMMANDS_H
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#define INCLUDE_CAMRTC_COMMANDS_H
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#define RTCPU_COMMAND(id, value) ((RTCPU_CMD_ ## id << 24U) | (value))
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#define RTCPU_GET_COMMAND_ID(value) (((value) >> 24U) & 0x7fU)
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#define RTCPU_GET_COMMAND_VALUE(value) ((value) & 0xffffffU)
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enum {
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RTCPU_CMD_INIT = 0U,
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RTCPU_CMD_FW_VERSION = 1U,
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RTCPU_CMD_IVC_READY = 2U,
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RTCPU_CMD_PING = 3U,
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RTCPU_CMD_PM_SUSPEND = 4U,
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RTCPU_CMD_FW_HASH = 5U,
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RTCPU_CMD_CH_SETUP = 6U,
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RTCPU_CMD_PREFIX = 0x7dU,
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RTCPU_CMD_DOORBELL = 0x7eU,
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RTCPU_CMD_ERROR = 0x7fU,
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};
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#define RTCPU_FW_DB_VERSION 0U
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#define RTCPU_FW_VERSION 1U
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#define RTCPU_FW_SM2_VERSION 2U
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#define RTCPU_FW_SM3_VERSION 3U
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/* SM4 firmware can restore itself after suspend */
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#define RTCPU_FW_SM4_VERSION 4U
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/* SM5 firmware supports IVC synchronization */
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#define RTCPU_FW_SM5_VERSION 5U
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/* SM5 driver supports IVC synchronization */
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#define RTCPU_DRIVER_SM5_VERSION 5U
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#define RTCPU_FW_CURRENT_VERSION (RTCPU_FW_SM5_VERSION)
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#define RTCPU_IVC_SANS_TRACE 1U
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#define RTCPU_IVC_WITH_TRACE 2U
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#define RTCPU_FW_HASH_SIZE 20U
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#define RTCPU_PM_SUSPEND_SUCCESS (0x100U)
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#define RTCPU_PM_SUSPEND_FAILURE (0x001U)
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#endif /* INCLUDE_CAMRTC_COMMANDS_H */
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