90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
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/*
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* include/uapi/linux/nvhost_nvcsi_ioctl.h
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*
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* Tegra NVCSI Driver
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#define __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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/* Bitmap
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*
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* | PHY_2 | PHY_1 | PHY_0 |
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* | 11 10 | 9 8 | 7 6 | 5 4 | 3 2 | 1 0 |
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* | CILB | CILA | CILB | CILA | CILB | CILA |
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*/
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#define PHY_0_CIL_A_IO0 0
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#define PHY_0_CIL_A_IO1 1
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#define PHY_0_CIL_B_IO0 2
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#define PHY_0_CIL_B_IO1 3
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#define PHY_1_CIL_A_IO0 4
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#define PHY_1_CIL_A_IO1 5
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#define PHY_1_CIL_B_IO0 6
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#define PHY_1_CIL_B_IO1 7
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#define PHY_2_CIL_A_IO0 8
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#define PHY_2_CIL_A_IO1 9
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#define PHY_2_CIL_B_IO0 10
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#define PHY_2_CIL_B_IO1 11
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#define PHY_3_CIL_A_IO0 12
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#define PHY_3_CIL_A_IO1 13
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#define PHY_3_CIL_B_IO0 14
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#define PHY_3_CIL_B_IO1 15
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#define NVCSI_PHY_CIL_NUM_LANE 16
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#define PHY_DPHY_MODE 0
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#define PHY_CPHY_MODE 1
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO0 (0x1 << PHY_0_CIL_A_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO1 (0x1 << PHY_0_CIL_A_IO1)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO0 (0x1 << PHY_0_CIL_B_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO1 (0x1 << PHY_0_CIL_B_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO0 (0x1 << PHY_1_CIL_A_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO1 (0x1 << PHY_1_CIL_A_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO0 (0x1 << PHY_1_CIL_B_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO1 (0x1 << PHY_1_CIL_B_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO0 (0x1 << PHY_2_CIL_A_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO1 (0x1 << PHY_2_CIL_A_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO0 (0x1 << PHY_2_CIL_B_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO1 (0x1 << PHY_2_CIL_B_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO0 (0x1 << PHY_3_CIL_A_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO1 (0x1 << PHY_3_CIL_A_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO0 (0x1 << PHY_3_CIL_B_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO1 (0x1 << PHY_3_CIL_B_IO1)
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#define NVCSI_PHY_NUM_BRICKS 4
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#define NVHOST_NVCSI_IOCTL_MAGIC 'N'
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#define NVHOST_NVCSI_IOCTL_DESKEW_SETUP _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 1, long)
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#define NVHOST_NVCSI_IOCTL_DESKEW_APPLY _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 2, long)
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#define NVHOST_NVCSI_IOCTL_PROD_APPLY _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 3, long)
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#endif
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