172 lines
7.3 KiB
C
172 lines
7.3 KiB
C
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/*
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* tegra210_adx_alt.h - Definitions for Tegra210 ADX driver
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_ADX_ALT_H__
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#define __TEGRA210_ADX_ALT_H__
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#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4
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#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4
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/* Register offsets from TEGRA210_ADX*_BASE */
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#define TEGRA210_ADX_AXBAR_RX_STATUS 0x0c
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#define TEGRA210_ADX_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_ADX_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_ADX_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_ADX_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_ADX_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA210_ADX_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_ADX_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_ADX_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_ADX_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_ADX_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_ADX_AXBAR_TX1_CIF_CTRL 0x60
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#define TEGRA210_ADX_AXBAR_TX2_CIF_CTRL 0x64
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#define TEGRA210_ADX_AXBAR_TX3_CIF_CTRL 0x68
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#define TEGRA210_ADX_AXBAR_TX4_CIF_CTRL 0x6c
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#define TEGRA210_ADX_ENABLE 0x80
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#define TEGRA210_ADX_SOFT_RESET 0x84
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#define TEGRA210_ADX_CG 0x88
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#define TEGRA210_ADX_STATUS 0x8c
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#define TEGRA210_ADX_INT_STATUS 0x90
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#define TEGRA210_ADX_CTRL 0xa4
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#define TEGRA210_ADX_IN_BYTE_EN0 0xa8
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#define TEGRA210_ADX_IN_BYTE_EN1 0xac
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#define TEGRA210_ADX_CYA 0xb0
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#define TEGRA210_ADX_DBG 0xb4
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL 0xb8
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_DATA 0xbc
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/* Fields in TEGRA210_ADX_AXBAR_RX_CIF_CTRL */
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/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_xbar_alt.h */
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/* Fields in TEGRA210_ADX_AXBAR_TX1_CIF_CTRL */
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/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_xbar_alt.h */
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/* Fields in TEGRA210_ADX_AXBAR_TX2_CIF_CTRL */
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/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_xbar_alt.h */
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/* Fields in TEGRA210_ADX_AXBAR_TX3_CIF_CTRL */
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/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_xbar_alt.h */
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/* Fields in TEGRA210_ADX_AXBAR_TX_CIF_CTRL */
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/* Uses field from TEGRA210_AUDIOCIF_CTRL_* in tegra210_xbar_alt.h */
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/* Fields in TEGRA210_ADX_ENABLE */
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#define TEGRA210_ADX_ENABLE_SHIFT 0
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#define TEGRA210_ADX_ENABLE_MASK (1 << TEGRA210_ADX_ENABLE_SHIFT)
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#define TEGRA210_ADX_EN (1 << TEGRA210_ADX_ENABLE_SHIFT)
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/* Fields inTEGRA210_ADX_CTRL */
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#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT 11
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#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX4_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT 10
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#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX3_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT 9
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#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX2_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT 8
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#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_MASK (1 << TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_EN (1 << TEGRA210_ADX_CTRL_TX1_FORCE_DISABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT 3
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#define TEGRA210_ADX_CTRL_TX4_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX4_EN (1 << TEGRA210_ADX_CTRL_TX4_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT 2
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#define TEGRA210_ADX_CTRL_TX3_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX3_EN (1 << TEGRA210_ADX_CTRL_TX3_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT 1
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#define TEGRA210_ADX_CTRL_TX2_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX2_EN (1 << TEGRA210_ADX_CTRL_TX2_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT 0
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#define TEGRA210_ADX_CTRL_TX1_ENABLE_MASK (1 << TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT)
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#define TEGRA210_ADX_CTRL_TX1_EN (1 << TEGRA210_ADX_CTRL_TX1_ENABLE_SHIFT)
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/* Fields in TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL */
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT 31
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_SHIFT 16
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_READ_COUNT_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT 14
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT 0
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#define TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_MASK (0xff << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT)
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/* Fields in TEGRA210_ADX_SOFT_RESET */
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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#define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
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/*
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* Those defines are not in register field.
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*/
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#define TEGRA210_ADX_NUM_OUTPUTS 4
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#define TEGRA210_ADX_RAM_DEPTH 16
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#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6
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#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2
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#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0
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enum {
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TEGRA210_ADX_TX_DISABLE,
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TEGRA210_ADX_TX_ENABLE,
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};
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enum {
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/* Code assumes that OUT_STREAM values of ADX start at 0 */
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/* OUT_STREAM# is equilvant to hw OUT_CH# */
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TEGRA210_ADX_OUT_STREAM0 = 0,
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TEGRA210_ADX_OUT_STREAM1,
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TEGRA210_ADX_OUT_STREAM2,
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TEGRA210_ADX_OUT_STREAM3,
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TEGRA210_ADX_IN_STREAM,
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TEGRA210_ADX_TOTAL_STREAM
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};
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struct tegra210_adx {
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struct regmap *regmap;
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unsigned int map[TEGRA210_ADX_RAM_DEPTH];
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unsigned int byte_mask[2];
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int input_channels;
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int output_channels[TEGRA210_ADX_NUM_OUTPUTS];
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};
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#endif
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