114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
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/*
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* tegra210_afc_alt.h - Definitions for Tegra210 AFC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_AFC_ALT_H__
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#define __TEGRA210_AFC_ALT_H__
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/*
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* AFC_AXBAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to AFC for playback.
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*/
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#define TEGRA210_AFC_AXBAR_RX_STATUS 0xc
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#define TEGRA210_AFC_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA210_AFC_AXBAR_RX_CYA 0x24
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/*
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* AFC_AXBAR_TX registers are with respect to AXBAR.
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* The data is going out of AFC for playback.
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*/
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#define TEGRA210_AFC_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_AFC_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_AFC_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_AFC_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_AFC_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_AFC_AXBAR_TX_CIF_CTRL 0x60
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#define TEGRA210_AFC_AXBAR_TX_CYA 0x64
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/* Register offsets from TEGRA210_AFC*_BASE */
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#define TEGRA210_AFC_ENABLE 0x80
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#define TEGRA210_AFC_SOFT_RESET 0x84
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#define TEGRA210_AFC_CG 0x88
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#define TEGRA210_AFC_STATUS 0x8c
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#define TEGRA210_AFC_INT_STATUS 0x90
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#define TEGRA210_AFC_INT_MASK 0x94
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#define TEGRA210_AFC_INT_SET 0x98
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#define TEGRA210_AFC_INT_CLEAR 0x9c
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/* Miscellaneous AFC registers */
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#define TEGRA210_AFC_DEST_I2S_PARAMS 0xa4
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#define TEGRA210_AFC_TXCIF_FIFO_PARAMS 0xa8
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#define TEGRA210_AFC_CLK_PPM_DIFF 0xac
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#define TEGRA210_AFC_DBG_CTRL 0xb0
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#define TEGRA210_AFC_TOTAL_SAMPLES 0xb4
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#define TEGRA210_AFC_DECIMATION_SAMPLES 0xb8
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#define TEGRA210_AFC_INTERPOLATION_SAMPLES 0xbc
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#define TEGRA210_AFC_DBG_INTERNAL 0xc0
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/* AFC coefficient registers */
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#define TEGRA210_AFC_LCOEF_1_4_0 0xc4
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#define TEGRA210_AFC_LCOEF_1_4_1 0xc8
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#define TEGRA210_AFC_LCOEF_1_4_2 0xcc
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#define TEGRA210_AFC_LCOEF_1_4_3 0xd0
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#define TEGRA210_AFC_LCOEF_1_4_4 0xd4
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#define TEGRA210_AFC_LCOEF_1_4_5 0xd8
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#define TEGRA210_AFC_LCOEF_2_4_0 0xdc
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#define TEGRA210_AFC_LCOEF_2_4_1 0xe0
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#define TEGRA210_AFC_LCOEF_2_4_2 0xe4
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#define TEGRA210_AFC_CYA 0xe8
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/* Fields in TEGRA210_AFC_ENABLE */
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#define TEGRA210_AFC_EN_SHIFT 0
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#define TEGRA210_AFC_EN (1 << TEGRA210_AFC_EN_SHIFT)
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#define TEGRA186_AFC_MODULE_SELECT_SHIFT 27
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#define TEGRA210_AFC_DEST_MODULE_ID_SHIFT 24
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#define TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT 16
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#define TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT 8
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#define AFC_CLK_PPM_DIFF 50
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struct tegra210_afc_soc_data {
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unsigned int num_i2s;
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bool flag_module_select;
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const struct snd_soc_codec_driver *afc_codec;
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};
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enum tegra210_afc_threshold_type {
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TH_DEFAULT, /* default thresholds */
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TH_NON_SFC, /* no SFC is in the path */
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TH_SFC, /* when SFC is in the path */
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TH_SFC_AMX, /* when both SFC and AMX in the path */
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TH_TYPE_COUNT,
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};
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struct tegra210_afc {
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struct regmap *regmap;
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const struct tegra210_afc_soc_data *soc_data;
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/* mandatory control to be set */
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unsigned int dest_module_num;
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unsigned int ppm_diff;
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unsigned int src_burst;
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unsigned int start_threshold;
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unsigned int threshold_type;
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};
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#endif
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