89 lines
3.2 KiB
C
89 lines
3.2 KiB
C
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/*
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* tegra210_ope_alt.h - Definitions for Tegra210 OPE driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_OPE_ALT_H__
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#define __TEGRA210_OPE_ALT_H__
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#include "tegra210_peq_alt.h"
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/* Register offsets from TEGRA210_OPE*_BASE */
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/*
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* OPE_AXBAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to OPE for playback.
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*/
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#define TEGRA210_OPE_AXBAR_RX_STATUS 0xc
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#define TEGRA210_OPE_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_OPE_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_OPE_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_OPE_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_OPE_AXBAR_RX_CIF_CTRL 0x20
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/*
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* OPE_AXBAR_TX registers are with respect to AXBAR.
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* The data is going out of OPE for playback.
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*/
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#define TEGRA210_OPE_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_OPE_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_OPE_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_OPE_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_OPE_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_OPE_AXBAR_TX_CIF_CTRL 0x60
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/* OPE Gloabal registers */
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#define TEGRA210_OPE_ENABLE 0x80
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#define TEGRA210_OPE_SOFT_RESET 0x84
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#define TEGRA210_OPE_CG 0x88
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#define TEGRA210_OPE_STATUS 0x8c
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#define TEGRA210_OPE_INT_STATUS 0x90
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#define TEGRA210_OPE_DIRECTION 0x94
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/* Fields for TEGRA210_OPE_ENABLE */
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#define TEGRA210_OPE_EN_SHIFT 0
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#define TEGRA210_OPE_EN (1 << TEGRA210_OPE_EN_SHIFT)
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/* Fields for TEGRA210_OPE_SOFT_RESET */
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#define TEGRA210_OPE_SOFT_RESET_SHIFT 0
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#define TEGRA210_OPE_SOFT_RESET_EN (1 << TEGRA210_OPE_SOFT_RESET_SHIFT)
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/* Fields for TEGRA210_OPE_DIRECTION */
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#define TEGRA210_OPE_DIRECTION_SHIFT 0
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#define TEGRA210_OPE_DIRECTION_MASK (1 << TEGRA210_OPE_DIRECTION_SHIFT)
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#define TEGRA210_OPE_DIRECTION_MBDRC_TO_PEQ (0 << TEGRA210_OPE_DIRECTION_SHIFT)
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#define TEGRA210_OPE_DIRECTION_PEQ_TO_MBDRC (1 << TEGRA210_OPE_DIRECTION_SHIFT)
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/* OPE register definitions end here */
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#define TEGRA210_PEQ_IORESOURCE_MEM 1
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#define TEGRA210_MBDRC_IORESOURCE_MEM 2
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struct tegra210_ope {
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struct regmap *regmap;
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struct regmap *peq_regmap;
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struct regmap *mbdrc_regmap;
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u32 peq_biquad_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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u32 peq_biquad_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH];
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};
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extern int tegra210_peq_init(struct platform_device *pdev, int id);
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extern int tegra210_peq_codec_init(struct snd_soc_codec *codec);
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extern void tegra210_peq_restore(struct tegra210_ope *ope);
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extern void tegra210_peq_save(struct tegra210_ope *ope);
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extern int tegra210_mbdrc_init(struct platform_device *pdev, int id);
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extern int tegra210_mbdrc_codec_init(struct snd_soc_codec *codec);
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extern int tegra210_mbdrc_hw_params(struct snd_soc_codec *codec);
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#endif
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