256 lines
12 KiB
C
256 lines
12 KiB
C
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/*
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* tegra210_spdif.h - Definitions for Tegra210 SPDIF driver
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_SPDIF_ALT_H__
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#define __TEGRA210_SPDIF_ALT_H__
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/* Register offsets from TEGRA_SPDIF_BASE */
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#define TEGRA210_SPDIF_CTRL 0x0
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#define TEGRA210_SPDIF_STROBE_CTRL 0x4
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#define TEGRA210_SPDIF_CIF_TXD_CTRL 0x08
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#define TEGRA210_SPDIF_CIF_RXD_CTRL 0x0C
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#define TEGRA210_SPDIF_CIF_TXU_CTRL 0x10
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#define TEGRA210_SPDIF_CIF_RXU_CTRL 0x14
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#define TEGRA210_SPDIF_CH_STA_RX_A 0x18
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#define TEGRA210_SPDIF_CH_STA_RX_B 0x1C
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#define TEGRA210_SPDIF_CH_STA_RX_C 0x20
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#define TEGRA210_SPDIF_CH_STA_RX_D 0x24
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#define TEGRA210_SPDIF_CH_STA_RX_E 0x28
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#define TEGRA210_SPDIF_CH_STA_RX_F 0x2C
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#define TEGRA210_SPDIF_CH_STA_TX_A 0x30
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#define TEGRA210_SPDIF_CH_STA_TX_B 0x34
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#define TEGRA210_SPDIF_CH_STA_TX_C 0x38
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#define TEGRA210_SPDIF_CH_STA_TX_D 0x3C
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#define TEGRA210_SPDIF_CH_STA_TX_E 0x40
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#define TEGRA210_SPDIF_CH_STA_TX_F 0x44
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#define TEGRA210_SPDIF_FLOWCTL_CTRL 0x70
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#define TEGRA210_SPDIF_TX_STEP 0x74
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#define TEGRA210_SPDIF_FLOW_STATUS 0x78
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#define TEGRA210_SPDIF_FLOW_TOTAL 0x7c
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#define TEGRA210_SPDIF_FLOW_OVER 0x80
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#define TEGRA210_SPDIF_FLOW_UNDER 0x84
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#define TEGRA210_SPDIF_LCOEF_1_4_0 0x88
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#define TEGRA210_SPDIF_LCOEF_1_4_1 0x8c
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#define TEGRA210_SPDIF_LCOEF_1_4_2 0x90
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#define TEGRA210_SPDIF_LCOEF_1_4_3 0x94
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#define TEGRA210_SPDIF_LCOEF_1_4_4 0x98
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#define TEGRA210_SPDIF_LCOEF_1_4_5 0x9c
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#define TEGRA210_SPDIF_LCOEF_2_4_0 0xa0
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#define TEGRA210_SPDIF_LCOEF_2_4_1 0xa4
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#define TEGRA210_SPDIF_LCOEF_2_4_2 0xa8
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/* Fields in TEGRA210_SPDIF_CTRL */
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#define TEGRA210_SPDIF_CTRL_FLOWCTL_EN_ENABLE (1<<31)
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#define TEGRA210_SPDIF_CTRL_CAP_LC_LEFT_CH (1<<30)
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#define TEGRA210_SPDIF_CTRL_RX_EN_ENABLE (1<<29)
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#define TEGRA210_SPDIF_CTRL_TX_EN_ENABLE (1<<28)
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#define TEGRA210_SPDIF_CTRL_TC_EN_ENABLE (1<<27)
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#define TEGRA210_SPDIF_CTRL_TU_EN_ENABLE (1<<26)
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#define TEGRA210_SPDIF_CTRL_IE_P_RSVD_ENABLE (1<<23)
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#define TEGRA210_SPDIF_CTRL_IE_B_RSVD_ENABLE (1<<22)
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#define TEGRA210_SPDIF_CTRL_IE_C_RSVD_ENABLE (1<<21)
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#define TEGRA210_SPDIF_CTRL_IE_U_RSVD_ENABLE (1<<20)
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#define TEGRA210_SPDIF_CTRL_LBK_EN_ENABLE_MASK (1<<15)
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#define TEGRA210_SPDIF_CTRL_LBK_EN_ENABLE_SHIFT 15
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#define TEGRA210_SPDIF_CTRL_PACK_ENABLE (1<<14)
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#define TEGRA210_SPDIF_BIT_MODE16 0
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#define TEGRA210_SPDIF_BIT_MODE20 1
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#define TEGRA210_SPDIF_BIT_MODE24 2
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#define TEGRA210_SPDIF_BIT_MODERAW 3
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT 12
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA210_SPDIF_BIT_MODE16 << TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA210_SPDIF_BIT_MODE20 << TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA210_SPDIF_BIT_MODE24 << TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA210_SPDIF_CTRL_BIT_MODE_RAW (TEGRA210_SPDIF_BIT_MODERAW << TEGRA210_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA210_SPDIF_CTRL_CG_EN_ENABLE (1<<11)
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#define TEGRA210_SPDIF_CTRL_OBS_SEL_SHIFT 8
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#define TEGRA210_SPDIF_CTRL_OBS_SEL_NASK (0x7 << TEGRA210_SPDIF_CTRL_OBS_SEL_SHIFT)
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#define TEGRA210_SPDIF_CTRL_SOFT_RESET_ENABLE (1<<7)
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/* Fields in TEGRA210_SPDIF_STROBE_CTRL */
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#define TEGRA210_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
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#define TEGRA210_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA210_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
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#define TEGRA210_SPDIF_STROBE_CTRL_STROBE (1<<15)
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#define TEGRA210_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
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#define TEGRA210_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA210_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
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#define TEGRA210_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
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#define TEGRA210_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA210_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
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/*
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* The 6-word receive channel data page buffer holds a block (192 frames) of
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* channel status information. The order of receive is from LSB to MSB
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* bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
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*/
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_A */
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_22050 0x4
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_24000 0x6
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_32000 0x3
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_44100 0x0
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_48000 0x2
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_88200 0x8
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_96000 0xA
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_176400 0xC
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#define TEGRA210_SPDIF_CH_STA_TX_A_SF_192000 0xE
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT 24
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK \
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(0xF << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_22050 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_22050 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_24000 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_24000 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_32000 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_44100 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_48000 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_88200 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_96000 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_176400 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000 \
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(TEGRA210_SPDIF_CH_STA_TX_A_SF_192000 << TEGRA210_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_B */
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_8000 0x6
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_11025 0xA
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_12000 0x2
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_16000 0x8
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_22050 0xB
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_24000 0x9
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_32000 0xC
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_44100 0xF
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_48000 0xD
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_88200 0x7
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_96000 0x5
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_176400 0x3
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#define TEGRA210_SPDIF_CH_STA_TX_B_SF_192000 0x1
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT 4
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK \
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(0xF << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_8000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_8000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_11025 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_11025 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_12000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_12000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_16000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_16000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_22050 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_22025 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_24000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_24000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_32000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_44100 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_48000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_88200 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_96000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_176400 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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#define TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000 \
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(TEGRA210_SPDIF_CH_STA_TX_B_SF_192000 << TEGRA210_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_C */
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_D */
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_E */
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/* Fields in TEGRA210_SPDIF_CH_STA_TX_F */
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/* Fields in TEGRA210_SPDIF_FLOWCTL_CTRL */
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#define TEGRA210_SPDIF_FLOWCTL_CTRL_FILTER_QUAD (1<<31)
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/* Fields in TEGRA210_SPDIF_TX_STEP */
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#define TEGRA210_SPDIF_TX_STEP_STEP_SIZE_SHIFT 0
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#define TEGRA210_SPDIF_TX_STEP_STEP_SIZE_MASK (0xffff << TEGRA210_SPDIF_TX_STEP_STEP_SIZE_SHIFT)
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/* Fields in TEGRA210_SPDIF_FLOW_STATUS */
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#define TEGRA210_SPDIF_FLOW_STATUS_COUNTER_EN_ENABLE (1<<1)
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#define TEGRA210_SPDIF_FLOW_STATUS_MONITOR_CLR_CLEAR (1<<2)
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#define TEGRA210_SPDIF_FLOW_STATUS_COUNTER_CLR_CLEAR (1<<3)
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#define TEGRA210_SPDIF_FLOW_STATUS_MONITOR_INT_EN_ENABLE (1<<4)
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#define TEGRA210_SPDIF_FLOW_STATUS_FLOW_OVERFLOW_OVER (1<<30)
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#define TEGRA210_SPDIF_FLOW_STATUS_FLOW_UNDERFLOW_UNDER (1<<31)
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/* Fields in TEGRA210_SPDIF_FLOW_TOTAL */
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/* Fields in TEGRA210_SPDIF_FLOW_OVER */
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/* Fields in TEGRA210_SPDIF_FLOW_UNDER */
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_0 */
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#define TEGRA210_SPDIF_LCOEF_1_4_0_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_0_COEF_MASK (0xffff << TEGRA30_TEGRA210_SPDIF_LCOEF_1_4_0_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_1 */
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#define TEGRA210_SPDIF_LCOEF_1_4_1_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_1_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_1_4_1_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_2 */
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#define TEGRA210_SPDIF_LCOEF_1_4_2_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_2_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_1_4_2_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_3 */
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#define TEGRA210_SPDIF_LCOEF_1_4_3_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_3_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_1_4_3_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_4 */
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#define TEGRA210_SPDIF_LCOEF_1_4_4_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_4_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_1_4_4_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_1_4_5 */
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#define TEGRA210_SPDIF_LCOEF_1_4_5_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_1_4_5_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_1_4_5_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_2_4_0 */
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#define TEGRA210_SPDIF_LCOEF_2_4_0_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_2_4_0_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_2_4_0_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_2_4_1 */
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#define TEGRA210_SPDIF_LCOEF_2_4_1_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_2_4_1_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_2_4_1_COEF_SHIFT)
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/* Fields in TEGRA210_SPDIF_LCOEF_2_4_2 */
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#define TEGRA210_SPDIF_LCOEF_2_4_2_COEF_SHIFT 0
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#define TEGRA210_SPDIF_LCOEF_2_4_2_COEF_MASK (0xffff << TEGRA210_SPDIF_LCOEF_2_4_2_COEF_SHIFT)
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struct tegra210_spdif {
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struct clk *clk_spdif_out;
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struct clk *clk_spdif_in;
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struct regmap *regmap;
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unsigned int loopback;
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};
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#endif
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