222 lines
7.8 KiB
C
222 lines
7.8 KiB
C
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/*
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* tegra210_xbar_alt.h - TEGRA210 XBAR registers
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_XBAR_ALT_H__
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#define __TEGRA210_XBAR_ALT_H__
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#define TEGRA210_XBAR_PART0_RX 0x0
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#define TEGRA210_XBAR_PART1_RX 0x200
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#define TEGRA210_XBAR_PART2_RX 0x400
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#define TEGRA210_XBAR_RX_STRIDE 0x4
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#define TEGRA210_XBAR_AUDIO_RX_COUNT 90
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/* This register repeats twice for each XBAR TX CIF */
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/* The fields in this register are 1 bit per XBAR RX CIF */
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/* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
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#define TEGRA210_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24
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/* Channel count minus 1 */
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20
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/* Channel count minus 1 */
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
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#define TEGRA210_AUDIOCIF_BITS_8 1
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#define TEGRA210_AUDIOCIF_BITS_16 3
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#define TEGRA210_AUDIOCIF_BITS_24 5
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#define TEGRA210_AUDIOCIF_BITS_32 7
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#define TEGRA210_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12
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#define TEGRA210_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8
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#define TEGRA210_AUDIOCIF_CTRL_EXPAND_SHIFT 6
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#define TEGRA210_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4
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#define TEGRA210_AUDIOCIF_CTRL_REPLICATE_SHIFT 3
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#define TEGRA210_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1
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#define TEGRA210_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0
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/* Fields in *AHUBRAMCTL_CTRL; used by different AHUB modules */
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_READ 0
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#define TEGRA210_AHUBRAMCTL_CTRL_RW_WRITE (1 << 14)
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#define TEGRA210_AHUBRAMCTL_CTRL_ADDR_INIT_EN (1 << 13)
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#define TEGRA210_AHUBRAMCTL_CTRL_SEQ_ACCESS_EN (1 << 12)
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#define TEGRA210_AHUBRAMCTL_CTRL_RAM_ADDR_MASK 0x1ff
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#define TEGRA210_NUM_DAIS 67
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#define TEGRA210_NUM_MUX_WIDGETS 50
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/* size of TEGRA210_ROUTES */
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#define TEGRA210_NUM_MUX_INPUT 54
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#define TEGRA186_NUM_DAIS 108
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#define TEGRA186_NUM_MUX_WIDGETS 79
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/* size of TEGRA_ROUTES + TEGRA186_ROUTES */
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#define TEGRA186_NUM_MUX_INPUT 82
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#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
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#define TEGRA186_XBAR_PART3_RX 0x600
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#define TEGRA186_XBAR_AUDIO_RX_COUNT 115
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#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +\
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
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#define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff
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#define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
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#define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
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#define TEGRA210_XBAR_REG_MASK_3 0x0
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#define TEGRA210_XBAR_UPDATE_MAX_REG 3
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#define TEGRA186_XBAR_REG_MASK_0 0xF3FFFFF
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#define TEGRA186_XBAR_REG_MASK_1 0x3F310F1F
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#define TEGRA186_XBAR_REG_MASK_2 0xFF3CF311
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#define TEGRA186_XBAR_REG_MASK_3 0x3F0F00FF
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#define TEGRA186_XBAR_UPDATE_MAX_REG 4
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#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
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/* T210 Modules Base address */
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#define T210_ADMAIF_BASE_ADDR 0x702d0000
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#define T210_I2S1_BASE_ADDR 0x702d1000
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#define T210_I2S2_BASE_ADDR 0x702d1100
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#define T210_I2S3_BASE_ADDR 0x702d1200
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#define T210_I2S4_BASE_ADDR 0x702d1300
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#define T210_I2S5_BASE_ADDR 0x702d1400
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#define T210_AMX1_BASE_ADDR 0x702d3000
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#define T210_AMX2_BASE_ADDR 0x702d3100
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#define T210_ADX1_BASE_ADDR 0x702d3800
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#define T210_ADX2_BASE_ADDR 0x702d3900
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#define T210_AFC1_BASE_ADDR 0x702d7000
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#define T210_AFC2_BASE_ADDR 0x702d7100
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#define T210_AFC3_BASE_ADDR 0x702d7200
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#define T210_AFC4_BASE_ADDR 0x702d7300
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#define T210_AFC5_BASE_ADDR 0x702d7400
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#define T210_AFC6_BASE_ADDR 0x702d7500
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#define T210_SFC1_BASE_ADDR 0x702d2000
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#define T210_SFC2_BASE_ADDR 0x702d2200
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#define T210_SFC3_BASE_ADDR 0x702d2400
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#define T210_SFC4_BASE_ADDR 0x702d2600
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#define T210_MVC1_BASE_ADDR 0x702da000
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#define T210_MVC2_BASE_ADDR 0x702da200
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#define T210_IQC1_BASE_ADDR 0x702de000
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#define T210_IQC2_BASE_ADDR 0x702de200
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#define T210_DMIC1_BASE_ADDR 0x702d4000
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#define T210_DMIC2_BASE_ADDR 0x702d4100
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#define T210_DMIC3_BASE_ADDR 0x702d4200
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#define T210_OPE1_BASE_ADDR 0x702d8000
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#define T210_OPE2_BASE_ADDR 0x702d8400
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#define T210_AMIXER1_BASE_ADDR 0x702dbb00
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/* T186 Modules Base address */
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#define T186_ADMAIF_BASE_ADDR 0x0290F000
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#define T186_I2S1_BASE_ADDR 0x02901000
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#define T186_I2S2_BASE_ADDR 0x02901100
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#define T186_I2S3_BASE_ADDR 0x02901200
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#define T186_I2S4_BASE_ADDR 0x02901300
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#define T186_I2S5_BASE_ADDR 0x02901400
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#define T186_I2S6_BASE_ADDR 0x02901500
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#define T186_AMX1_BASE_ADDR 0x02903000
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#define T186_AMX2_BASE_ADDR 0x02903100
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#define T186_AMX3_BASE_ADDR 0x02903200
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#define T186_AMX4_BASE_ADDR 0x02903300
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#define T186_ADX1_BASE_ADDR 0x02903800
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#define T186_ADX2_BASE_ADDR 0x02903900
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#define T186_ADX3_BASE_ADDR 0x02903a00
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#define T186_ADX4_BASE_ADDR 0x02903b00
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#define T186_AFC1_BASE_ADDR 0x02907000
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#define T186_AFC2_BASE_ADDR 0x02907100
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#define T186_AFC3_BASE_ADDR 0x02907200
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#define T186_AFC4_BASE_ADDR 0x02907300
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#define T186_AFC5_BASE_ADDR 0x02907400
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#define T186_AFC6_BASE_ADDR 0x02907500
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#define T186_SFC1_BASE_ADDR 0x02902000
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#define T186_SFC2_BASE_ADDR 0x02902200
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#define T186_SFC3_BASE_ADDR 0x02902400
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#define T186_SFC4_BASE_ADDR 0x02902600
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#define T186_MVC1_BASE_ADDR 0x0290A000
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#define T186_MVC2_BASE_ADDR 0x0290A200
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#define T186_IQC1_BASE_ADDR 0x0290E000
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#define T186_IQC2_BASE_ADDR 0x0290E200
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#define T186_DMIC1_BASE_ADDR 0x02904000
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#define T186_DMIC2_BASE_ADDR 0x02904100
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#define T186_DMIC3_BASE_ADDR 0x02904200
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#define T186_DMIC4_BASE_ADDR 0x02904300
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#define T186_OPE1_BASE_ADDR 0x02908000
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#define T186_AMIXER1_BASE_ADDR 0x0290BB00
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#define T186_ASRC1_BASE_ADDR 0x02910000
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#define T186_ARAD1_BASE_ADDR 0x0290E400
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#define T186_DSPK1_BASE_ADDR 0x02905000
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#define T186_DSPK2_BASE_ADDR 0x02905100
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struct tegra210_xbar_cif_conf {
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unsigned int threshold;
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unsigned int audio_channels;
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unsigned int client_channels;
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unsigned int audio_bits;
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unsigned int client_bits;
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unsigned int expand;
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unsigned int stereo_conv;
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union {
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unsigned int fifo_size_downshift;
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unsigned int replicate;
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};
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unsigned int truncate;
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unsigned int mono_conv;
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};
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struct tegra_xbar_soc_data {
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const struct regmap_config *regmap_config;
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unsigned int mask[4];
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unsigned int reg_count;
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unsigned int reg_offset;
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int (*xbar_registration)(struct platform_device *pdev);
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};
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struct tegra_xbar {
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struct clk *clk;
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struct regmap *regmap;
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const struct tegra_xbar_soc_data *soc_data;
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};
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/* Extension of soc_bytes structure defined in sound/soc.h */
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struct tegra_soc_bytes {
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struct soc_bytes soc;
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u32 shift; /* Used as offset for ahub ram related programing */
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};
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void tegra210_xbar_set_cif(struct regmap *regmap, unsigned int reg,
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struct tegra210_xbar_cif_conf *conf);
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void tegra210_xbar_write_ahubram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int reg_data, unsigned int ram_offset,
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unsigned int *data, size_t size);
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void tegra210_xbar_read_ahubram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int reg_data, unsigned int ram_offset,
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unsigned int *data, size_t size);
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/* Utility structures for using mixer control of type snd_soc_bytes */
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#define TEGRA_SOC_BYTES_EXT(xname, xbase, xregs, xshift, xmask, \
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xhandler_get, xhandler_put, xinfo) \
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{.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = xinfo, .get = xhandler_get, .put = xhandler_put, \
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.private_value = ((unsigned long)&(struct tegra_soc_bytes) \
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{.soc.base = xbase, .soc.num_regs = xregs, .soc.mask = xmask, \
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.shift = xshift })}
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#endif
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