403 lines
10 KiB
C
403 lines
10 KiB
C
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/*
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* tegra210_iqc.c - Tegra210 IQC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include <linux/tegra-soc.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_iqc_alt.h"
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#define DRV_NAME "tegra210-iqc"
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static const struct reg_default tegra210_iqc_reg_defaults[] = {
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{ TEGRA210_IQC_AXBAR_TX_INT_MASK, 0x0000000f},
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{ TEGRA210_IQC_AXBAR_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_IQC_CG, 0x1},
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{ TEGRA210_IQC_CTRL, 0x80000020},
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};
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static int tegra210_iqc_runtime_suspend(struct device *dev)
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{
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struct tegra210_iqc *iqc = dev_get_drvdata(dev);
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regcache_cache_only(iqc->regmap, true);
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regcache_mark_dirty(iqc->regmap);
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#ifndef CONFIG_MACH_GRENADA
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clk_disable_unprepare(iqc->clk_iqc);
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#endif
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return 0;
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}
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static int tegra210_iqc_runtime_resume(struct device *dev)
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{
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struct tegra210_iqc *iqc = dev_get_drvdata(dev);
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int ret;
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#ifndef CONFIG_MACH_GRENADA
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ret = clk_prepare_enable(iqc->clk_iqc);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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#endif
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regcache_cache_only(iqc->regmap, false);
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regcache_sync(iqc->regmap);
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return 0;
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}
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static int tegra210_iqc_set_audio_cif(struct tegra210_iqc *iqc,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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int channels, audio_bits;
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struct tegra210_xbar_cif_conf cif_conf;
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channels = params_channels(params);
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if (channels < 2)
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return -EINVAL;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra210_xbar_set_cif(iqc->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_iqc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_iqc *iqc = snd_soc_dai_get_drvdata(dai);
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int ret;
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/* set IQC tx cif */
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ret = tegra210_iqc_set_audio_cif(iqc, params,
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TEGRA210_IQC_AXBAR_TX_CIF_CTRL +
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(dai->id * TEGRA210_IQC_AXBAR_TX_STRIDE));
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if (ret) {
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dev_err(dev, "Can't set IQC TX CIF: %d\n", ret);
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return ret;
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}
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/* disable timestamp */
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if (!iqc->timestamp_enable)
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regmap_update_bits(iqc->regmap, TEGRA210_IQC_CTRL,
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TEGRA210_IQC_TIMESTAMP_MASK,
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~(TEGRA210_IQC_TIMESTAMP_EN));
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/* set the IQC data offset */
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if (iqc->data_offset)
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regmap_update_bits(iqc->regmap, TEGRA210_IQC_CTRL,
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TEGRA210_IQC_DATA_OFFSET_MASK,
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iqc->data_offset);
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return ret;
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}
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static struct snd_soc_dai_ops tegra210_iqc_dai_ops = {
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.hw_params = tegra210_iqc_hw_params,
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};
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#define IN_DAI(id) \
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{ \
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.name = "DAP", \
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.playback = { \
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.stream_name = "DAP" #id " Receive", \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_96000, \
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.formats = SNDRV_PCM_FMTBIT_S16_LE, \
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}, \
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}
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#define OUT_DAI(id) \
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{ \
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.name = "CIF", \
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.capture = { \
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.stream_name = "CIF" #id " Transmit", \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_96000, \
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.formats = SNDRV_PCM_FMTBIT_S16_LE, \
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}, \
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.ops = &tegra210_iqc_dai_ops, \
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}
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static struct snd_soc_dai_driver tegra210_iqc_dais[] = {
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OUT_DAI(1),
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OUT_DAI(2),
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IN_DAI(1),
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IN_DAI(2),
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};
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static const struct snd_kcontrol_new tegra210_iqc_controls[] = {
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SOC_SINGLE("IQC Enable", TEGRA210_IQC_ENABLE, 0, 1, 0),
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};
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static const struct snd_soc_dapm_widget tegra210_iqc_widgets[] = {
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SND_SOC_DAPM_AIF_IN("IQC RX1", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_IN("IQC RX2", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_OUT("IQC TX1", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_OUT("IQC TX2", NULL, 0, SND_SOC_NOPM,
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0, 0),
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};
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static const struct snd_soc_dapm_route tegra210_iqc_routes[] = {
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{ "IQC RX1", NULL, "DAP1 Receive" },
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{ "IQC TX1", NULL, "IQC RX1" },
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{ "CIF1 Transmit", NULL, "IQC TX1" },
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{ "IQC RX2", NULL, "DAP2 Receive" },
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{ "IQC TX2", NULL, "IQC RX2" },
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{ "CIF2 Transmit", NULL, "IQC TX2" },
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};
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static struct snd_soc_codec_driver tegra210_iqc_codec = {
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.idle_bias_off = 1,
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.component_driver = {
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.dapm_widgets = tegra210_iqc_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_iqc_widgets),
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.dapm_routes = tegra210_iqc_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_iqc_routes),
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.controls = tegra210_iqc_controls,
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.num_controls = ARRAY_SIZE(tegra210_iqc_controls),
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},
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};
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static bool tegra210_iqc_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_IQC_AXBAR_TX_INT_MASK:
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case TEGRA210_IQC_AXBAR_TX_INT_SET:
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case TEGRA210_IQC_AXBAR_TX_INT_CLEAR:
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case TEGRA210_IQC_AXBAR_TX_CIF_CTRL:
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case TEGRA210_IQC_ENABLE:
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case TEGRA210_IQC_SOFT_RESET:
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case TEGRA210_IQC_CG:
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case TEGRA210_IQC_CTRL:
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case TEGRA210_IQC_CYA:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_iqc_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_IQC_AXBAR_TX_STATUS:
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case TEGRA210_IQC_AXBAR_TX_INT_STATUS:
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case TEGRA210_IQC_AXBAR_TX_INT_MASK:
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case TEGRA210_IQC_AXBAR_TX_INT_SET:
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case TEGRA210_IQC_AXBAR_TX_INT_CLEAR:
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case TEGRA210_IQC_AXBAR_TX_CIF_CTRL:
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case TEGRA210_IQC_ENABLE:
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case TEGRA210_IQC_SOFT_RESET:
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case TEGRA210_IQC_CG:
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case TEGRA210_IQC_STATUS:
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case TEGRA210_IQC_INT_STATUS:
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case TEGRA210_IQC_CTRL:
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case TEGRA210_IQC_TIME_STAMP_STATUS_0:
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case TEGRA210_IQC_TIME_STAMP_STATUS_1:
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case TEGRA210_IQC_WS_EDGE_STATUS:
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case TEGRA210_IQC_CYA:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_iqc_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_IQC_AXBAR_TX_CIF_CTRL:
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case TEGRA210_IQC_ENABLE:
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case TEGRA210_IQC_CTRL:
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return true;
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default:
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return false;
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};
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}
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static const struct regmap_config tegra210_iqc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_IQC_CYA,
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.writeable_reg = tegra210_iqc_wr_reg,
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.readable_reg = tegra210_iqc_rd_reg,
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.volatile_reg = tegra210_iqc_volatile_reg,
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.reg_defaults = tegra210_iqc_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_iqc_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static const struct of_device_id tegra210_iqc_of_match[] = {
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{ .compatible = "nvidia,tegra210-iqc" },
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{},
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};
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static int tegra210_iqc_platform_probe(struct platform_device *pdev)
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{
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struct tegra210_iqc *iqc;
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struct resource *mem;
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void __iomem *regs;
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int ret = 0;
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const struct of_device_id *match;
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match = of_match_device(tegra210_iqc_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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return -ENODEV;
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}
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iqc = devm_kzalloc(&pdev->dev, sizeof(*iqc), GFP_KERNEL);
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if (!iqc)
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return -ENOMEM;
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dev_set_drvdata(&pdev->dev, iqc);
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if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
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iqc->clk_iqc = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(iqc->clk_iqc)) {
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dev_err(&pdev->dev, "Can't retrieve iqc clock\n");
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return PTR_ERR(iqc->clk_iqc);
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}
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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iqc->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra210_iqc_regmap_config);
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if (IS_ERR(iqc->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(iqc->regmap);
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}
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regcache_cache_only(iqc->regmap, true);
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ret = of_property_read_u32(pdev->dev.of_node,
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"nvidia,ahub-iqc-id",
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&pdev->dev.id);
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if (ret < 0) {
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dev_err(&pdev->dev, "Missing property nvidia,ahub-iqc-id\n");
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return ret;
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}
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if (of_property_read_u32(pdev->dev.of_node,
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"timestamp-enable",
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&iqc->timestamp_enable) < 0) {
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dev_dbg(&pdev->dev,
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"Missing property timestamp-enable for IQC\n");
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iqc->timestamp_enable = 1;
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}
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if (of_property_read_u32(pdev->dev.of_node,
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"data-offset",
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&iqc->data_offset) < 0) {
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dev_dbg(&pdev->dev,
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"Missing property data-offset for IQC\n");
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iqc->data_offset = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
pm_runtime_enable(&pdev->dev);
|
||
|
|
ret = snd_soc_register_codec(&pdev->dev, &tegra210_iqc_codec,
|
||
|
|
tegra210_iqc_dais,
|
||
|
|
ARRAY_SIZE(tegra210_iqc_dais));
|
||
|
|
if (ret != 0) {
|
||
|
|
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra210_iqc_platform_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct tegra210_iqc *iqc = dev_get_drvdata(&pdev->dev);
|
||
|
|
|
||
|
|
snd_soc_unregister_codec(&pdev->dev);
|
||
|
|
|
||
|
|
pm_runtime_disable(&pdev->dev);
|
||
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
||
|
|
tegra210_iqc_runtime_suspend(&pdev->dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dev_pm_ops tegra210_iqc_pm_ops = {
|
||
|
|
SET_RUNTIME_PM_OPS(tegra210_iqc_runtime_suspend,
|
||
|
|
tegra210_iqc_runtime_resume, NULL)
|
||
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||
|
|
pm_runtime_force_resume)
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver tegra210_iqc_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = DRV_NAME,
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = tegra210_iqc_of_match,
|
||
|
|
.pm = &tegra210_iqc_pm_ops,
|
||
|
|
},
|
||
|
|
.probe = tegra210_iqc_platform_probe,
|
||
|
|
.remove = tegra210_iqc_platform_remove,
|
||
|
|
};
|
||
|
|
module_platform_driver(tegra210_iqc_driver)
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Arun S L <aruns@nvidia.com>");
|
||
|
|
MODULE_DESCRIPTION("Tegra210 IQC ASoC driver");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
||
|
|
MODULE_DEVICE_TABLE(of, tegra210_iqc_of_match);
|