392 lines
12 KiB
C
392 lines
12 KiB
C
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/*
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* tegra210_peq_alt.c - Tegra210 PEQ driver
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_ope_alt.h"
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#include "tegra210_peq_alt.h"
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static const struct reg_default tegra210_peq_reg_defaults[] = {
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{ TEGRA210_PEQ_CONFIG, 0x00000013},
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{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, 0x00004000},
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{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, 0x00004000},
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};
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/* Default PEQ filter parameters for a 5-stage biquad*/
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static const int biquad_init_stage = 5;
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static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
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1495012349, /* pre-gain */
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/* Gains : b0, b1, a0, a1, a2 */
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536870912, -1073741824, 536870912, 2143508246, -1069773768, /* band-0 */
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134217728, -265414508, 131766272, 2140402222, -1071252997, /* band-1 */
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268435456, -233515765, -33935948, 1839817267, -773826124, /* band-2 */
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536870912, -672537913, 139851540, 1886437554, -824433167, /* band-3 */
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268435456, -114439279, 173723964, 205743566, 278809729, /* band-4 */
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1, 0, 0, 0, 0, /* band-5 */
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1, 0, 0, 0, 0, /* band-6 */
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1, 0, 0, 0, 0, /* band-7 */
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1, 0, 0, 0, 0, /* band-8 */
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1, 0, 0, 0, 0, /* band-9 */
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1, 0, 0, 0, 0, /* band-10 */
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1, 0, 0, 0, 0, /* band-11 */
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963423114, /* post-gain */
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};
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static const u32 biquad_init_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH] = {
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23, /* pre-shift */
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30, 30, 30, 30, 30, 0, 0, 0, 0, 0, 0, 0, /* shift for bands */
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28, /* post-shift */
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};
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static s32 biquad_coeff_buffer[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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static int tegra210_peq_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_ope *ope = snd_soc_codec_get_drvdata(codec);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val;
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regmap_read(ope->peq_regmap, mc->reg, &val);
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ucontrol->value.integer.value[0] = (val >> mc->shift) & mask;
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if (mc->invert)
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ucontrol->value.integer.value[0] =
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mc->max - ucontrol->value.integer.value[0];
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return 0;
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}
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static int tegra210_peq_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_ope *ope = snd_soc_codec_get_drvdata(codec);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val;
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val = (ucontrol->value.integer.value[0] & mask);
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if (mc->invert)
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val = mc->max - val;
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val = val << mc->shift;
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return regmap_update_bits(ope->peq_regmap, mc->reg,
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(mask << mc->shift), val);
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}
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static int tegra210_peq_ahub_ram_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_ope *ope = snd_soc_codec_get_drvdata(codec);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + codec->component.val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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pm_runtime_get_sync(codec->dev);
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tegra210_xbar_read_ahubram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(codec->dev);
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for (i = 0; i < params->soc.num_regs; i++)
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ucontrol->value.integer.value[i] = (long)data[i];
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return 0;
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}
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static int tegra210_peq_ahub_ram_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_ope *ope = snd_soc_codec_get_drvdata(codec);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + codec->component.val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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for (i = 0; i < params->soc.num_regs; i++)
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data[i] = (s32)ucontrol->value.integer.value[i];
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pm_runtime_get_sync(codec->dev);
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tegra210_xbar_write_ahubram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(codec->dev);
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return 0;
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}
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static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct soc_bytes *params = (void *)kcontrol->private_value;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->value.integer.min = -0x7fffffff;
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uinfo->value.integer.max = 0x7fffffff;
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uinfo->count = params->num_regs;
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return 0;
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}
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#define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad gain params", \
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, \
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \
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tegra210_peq_ahub_ram_get, tegra210_peq_ahub_ram_put, \
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tegra210_peq_param_info)
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#define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad shift params", \
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, \
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \
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tegra210_peq_ahub_ram_get, tegra210_peq_ahub_ram_put, \
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tegra210_peq_param_info)
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static const struct snd_kcontrol_new tegra210_peq_controls[] = {
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SOC_SINGLE_EXT("peq active", TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONFIG_MODE_SHIFT, 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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SOC_SINGLE_EXT("peq biquad stages", TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT,
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TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(0),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(1),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(2),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(3),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(4),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(5),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(6),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(7),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(0),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(1),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(2),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(3),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(4),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(5),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(6),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(7),
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};
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static bool tegra210_peq_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_CG:
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case TEGRA210_PEQ_CONFIG:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_peq_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_CG:
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case TEGRA210_PEQ_STATUS:
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case TEGRA210_PEQ_CONFIG:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_peq_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_STATUS:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_peq_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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};
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}
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static const struct regmap_config tegra210_peq_regmap_config = {
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.name = "peq",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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.writeable_reg = tegra210_peq_wr_reg,
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.readable_reg = tegra210_peq_rd_reg,
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.volatile_reg = tegra210_peq_volatile_reg,
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.precious_reg = tegra210_peq_precious_reg,
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.reg_defaults = tegra210_peq_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_peq_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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void tegra210_peq_restore(struct tegra210_ope *ope)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_xbar_write_ahubram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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tegra210_xbar_write_ahubram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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}
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EXPORT_SYMBOL_GPL(tegra210_peq_restore);
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void tegra210_peq_save(struct tegra210_ope *ope)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_xbar_read_ahubram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
|
||
|
|
(u32 *)&ope->peq_biquad_gains,
|
||
|
|
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
|
||
|
|
|
||
|
|
tegra210_xbar_read_ahubram(ope->peq_regmap,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
|
||
|
|
(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
|
||
|
|
(u32 *)&ope->peq_biquad_shifts,
|
||
|
|
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(tegra210_peq_save);
|
||
|
|
|
||
|
|
int tegra210_peq_codec_init(struct snd_soc_codec *codec)
|
||
|
|
{
|
||
|
|
struct tegra210_ope *ope = snd_soc_codec_get_drvdata(codec);
|
||
|
|
int i = 0;
|
||
|
|
|
||
|
|
pm_runtime_get_sync(codec->dev);
|
||
|
|
regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CONFIG,
|
||
|
|
TEGRA210_PEQ_CONFIG_MODE_MASK,
|
||
|
|
0 << TEGRA210_PEQ_CONFIG_MODE_SHIFT);
|
||
|
|
regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CONFIG,
|
||
|
|
TEGRA210_PEQ_CONfIG_BIQUAD_STAGES_MASK,
|
||
|
|
(biquad_init_stage - 1) <<
|
||
|
|
TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT);
|
||
|
|
|
||
|
|
/* Initialize PEQ AHUB RAM with default params */
|
||
|
|
for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
|
||
|
|
/* Set default gain params */
|
||
|
|
tegra210_xbar_write_ahubram(ope->peq_regmap,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
|
||
|
|
(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
|
||
|
|
(u32 *)&biquad_init_gains,
|
||
|
|
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
|
||
|
|
|
||
|
|
/* Set default shift params */
|
||
|
|
tegra210_xbar_write_ahubram(ope->peq_regmap,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
|
||
|
|
TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
|
||
|
|
(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
|
||
|
|
(u32 *)&biquad_init_shifts,
|
||
|
|
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
|
||
|
|
}
|
||
|
|
pm_runtime_put_sync(codec->dev);
|
||
|
|
|
||
|
|
snd_soc_add_codec_controls(codec, tegra210_peq_controls,
|
||
|
|
ARRAY_SIZE(tegra210_peq_controls));
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(tegra210_peq_codec_init);
|
||
|
|
|
||
|
|
int tegra210_peq_init(struct platform_device *pdev, int id)
|
||
|
|
{
|
||
|
|
struct tegra210_ope *ope = dev_get_drvdata(&pdev->dev);
|
||
|
|
struct resource *mem;
|
||
|
|
void __iomem *regs;
|
||
|
|
|
||
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, id);
|
||
|
|
regs = devm_ioremap_resource(&pdev->dev, mem);
|
||
|
|
if (IS_ERR(regs))
|
||
|
|
return PTR_ERR(regs);
|
||
|
|
ope->peq_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||
|
|
&tegra210_peq_regmap_config);
|
||
|
|
if (IS_ERR(ope->peq_regmap)) {
|
||
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
||
|
|
return PTR_ERR(ope->peq_regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(tegra210_peq_init);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
|
||
|
|
MODULE_DESCRIPTION("Tegra210 PEQ module");
|
||
|
|
MODULE_LICENSE("GPL");
|