/* * arch/arm/boot/dts/panel-n-wqxga-6-0.dtsi * * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include #include / { host1x { dsi { panel_n_wqxga_6_0: panel-n-wqxga-6-0 { compatible = "n,wqxga-6-0"; nvidia,dsi-instance = ; nvidia,dsi-n-data-lanes = <4>; nvidia,dsi-pixel-format = ; nvidia,dsi-refresh-rate = <60>; nvidia,dsi-video-data-type = ; nvidia,dsi-video-clock-mode = ; nvidia,enable-link-compression; nvidia,enable-block-pred; nvidia,slice-height = <32>; nvidia,num-of-slices = <2>; nvidia,comp-rate = <8>; nvidia,dsi-controller-vs = ; nvidia,dsi-virtual-channel = ; nvidia,dsi-panel-reset = ; nvidia,dsi-suspend-stop-stream-late = ; nvidia,dsi-init-cmd = /* Long Packet: */ /* Short Packet: */ /* For DSI packets each DT cell is interpreted as u8 not u32 */ <0x0 DSI_DCS_WRITE_1_PARAM 0xFF 0x10 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0xBB 0x10 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0xC0 0x03 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0xE5 0x00 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0xFF 0x10 0x0>, , <0x0 DSI_DCS_LONG_WRITE 0x11 0x0 0x0 0xC1 0x09 0x20 0x00 0x20 0x02 0x00 0x02 0x68 0x03 0x87 0x00 0x0A 0x03 0x19 0x02 0x63 0x0 0x0>, <0x0 DSI_DCS_LONG_WRITE 0x3 0x0 0x0 0xC2 0x10 0xF0 0x0 0x0>, <0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>, , <0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>, , <0x0 DSI_DCS_WRITE_1_PARAM 0x51 0xAA 0x0>; nvidia,dsi-n-init-cmd = <19>; nvidia,dsi-early-suspend-cmd = , , , ; nvidia,dsi-n-early-suspend-cmd = <4>; nvidia,dsi-pkt-seq = , , , , , ; disp-default-out { nvidia,out-type = ; nvidia,out-width = <200>; /* Fix me: Correct out-width and out-height parameters */ nvidia,out-height = <232>; nvidia,out-flags = ; nvidia,out-parent-clk = "pll_d_out0"; nvidia,out-xres = <1440>; nvidia,out-yres = <2560>; }; display-timings { 1440x2560-32-60Hz { clock-frequency = <253872000>; hactive = <1440>; vactive = <2560>; hfront-porch = <170>; hback-porch = <20>; hsync-len = <10>; vfront-porch = <10>; vback-porch = <8>; vsync-len = <2>; nvidia,h-ref-to-sync = <4>; nvidia,v-ref-to-sync = <1>; }; }; vrr-settings { nvidia,vrr_min_fps = <30>; }; }; }; }; };