/*
 * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/*
 * This is the t19x specific component of the new SID dt-binding.
 */
#define TEGRA_SID_RCE		0x2a	/* 42 */
#define TEGRA_SID_RCE_VM2	0x2b	/* 43 */

#define TEGRA_SID_RCE_RM	0x2F	/* 47 */
#define TEGRA_SID_VIFALC	0x30	/* 48 */
#define TEGRA_SID_ISPFALC	0x31	/* 49 */

#define TEGRA_SID_MIU		0x50	/* 80 */

#define TEGRA_SID_NVDLA0	0x51	/* 81 */
#define TEGRA_SID_NVDLA1	0x52	/* 82 */

#define TEGRA_SID_PVA0		0x53	/* 83 */
#define TEGRA_SID_PVA1		0x54	/* 84 */

#define TEGRA_SID_NVENC1	0x55	/* 85 */

#define TEGRA_SID_PCIE0		0x56	/* 86 */
#define TEGRA_SID_PCIE1		0x57	/* 87 */
#define TEGRA_SID_PCIE2		0x58	/* 88 */
#define TEGRA_SID_PCIE3		0x59	/* 89 */
#define TEGRA_SID_PCIE4		0x5A	/* 90 */
#define TEGRA_SID_PCIE5		0x5B	/* 91 */

#define TEGRA_SID_NVDEC1	0x5C	/* 92 */

#define TEGRA_SID_VI_VM2	0x64	/* 100 */