/* * IOMMU API for ARM architected SMMU implementations. * * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. * * NVIDIA Corporation and its licensors retain all intellectual property * and proprietary rights in and to this software and related documentation * and any modifications thereto. Any use, reproduction, disclosure or * distribution of this software and related documentation without an express * license agreement from NVIDIA Corporation is strictly prohibited. */ #ifndef _ARM_SMMU_REGS_H #define _ARM_SMMU_REGS_H /* SMMU global address space */ #define ARM_SMMU_GR0(smmu) ((smmu)->base) #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) #define ARM_SMMU_PME(smmu) ((smmu)->base + (3 << (smmu)->pgshift)) /* * SMMU global address space with conditional offset to access secure * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, * nsGFSYNR0: 0x450) */ #define ARM_SMMU_GR0_NS(smmu) \ ((smmu)->base + \ ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ ? 0x400 : 0)) /* Page table bits */ #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) #if PAGE_SIZE == SZ_4K #define ARM_SMMU_PTE_CONT_ENTRIES 16 #elif PAGE_SIZE == SZ_64K #define ARM_SMMU_PTE_CONT_ENTRIES 32 #else #define ARM_SMMU_PTE_CONT_ENTRIES 1 #endif #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) /* Stage-1 PTE */ #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) /* Stage-2 PTE */ #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) /* Configuration registers */ #define ARM_SMMU_GR0_sCR0 0x0 #define ARM_SMMU_GR0_sCR2 0x8 #define ARM_SMMU_GR0_sACR 0x10 #define sCR0_CLIENTPD (1 << 0) #define sCR0_GFRE (1 << 1) #define sCR0_GFIE (1 << 2) #define sCR0_GCFGFRE (1 << 4) #define sCR0_GCFGFIE (1 << 5) #define sCR0_USFCFG (1 << 10) #define sCR0_VMIDPNE (1 << 11) #define sCR0_PTM (1 << 12) #define sCR0_FB (1 << 13) #define sCR0_BSU_SHIFT 14 #define sCR0_BSU_MASK 0x3 /* Identification registers */ #define ARM_SMMU_GR0_ID0 0x20 #define ARM_SMMU_GR0_ID1 0x24 #define ARM_SMMU_GR0_ID2 0x28 #define ARM_SMMU_GR0_ID3 0x2c #define ARM_SMMU_GR0_ID4 0x30 #define ARM_SMMU_GR0_ID5 0x34 #define ARM_SMMU_GR0_ID6 0x38 #define ARM_SMMU_GR0_ID7 0x3c #define ARM_SMMU_GR0_sGFAR 0x40 #define ARM_SMMU_GR0_sGFSR 0x48 #define ARM_SMMU_GR0_sGFSYNR0 0x50 #define ARM_SMMU_GR0_sGFSYNR1 0x54 #define ARM_SMMU_GR0_sGFSYNR2 0x58 #define ARM_SMMU_GR0_nsCR0 0x400 #define ARM_SMMU_GR0_nsGFAR 0x440 #define ARM_SMMU_GR0_nsGFSR 0x448 #define ARM_SMMU_GR0_nsGFSYNR0 0x450 #define ARM_SMMU_GR0_nsGFSYNR1 0x454 #define ARM_SMMU_GR0_nsGFSYNR2 0x458 #define ARM_SMMU_GR0_PIDR0 0xfe0 #define ARM_SMMU_GR0_PIDR1 0xfe4 #define ARM_SMMU_GR0_PIDR2 0xfe8 #define ID0_S1TS (1 << 30) #define ID0_S2TS (1 << 29) #define ID0_NTS (1 << 28) #define ID0_SMS (1 << 27) #define ID0_PTFS_SHIFT 24 #define ID0_PTFS_MASK 0x2 #define ID0_PTFS_V8_ONLY 0x2 #define ID0_CTTW (1 << 14) #define ID0_NUMIRPT_SHIFT 16 #define ID0_NUMIRPT_MASK 0xff #define ID0_NUMSIDB_SHIFT 9 #define ID0_NUMSIDB_MASK 0xf #define ID0_NUMSMRG_SHIFT 0 #define ID0_NUMSMRG_MASK 0xff #define ID1_PAGESIZE (1 << 31) #define ID1_NUMPAGENDXB_SHIFT 28 #define ID1_NUMPAGENDXB_MASK 7 #define ID1_NUMS2CB_SHIFT 16 #define ID1_NUMS2CB_MASK 0xff #define ID1_NUMCB_SHIFT 0 #define ID1_NUMCB_MASK 0xff #define ID2_OAS_SHIFT 4 #define ID2_OAS_MASK 0xf #define ID2_IAS_SHIFT 0 #define ID2_IAS_MASK 0xf #define ID2_UBS_SHIFT 8 #define ID2_UBS_MASK 0xf #define ID2_PTFS_4K (1 << 12) #define ID2_PTFS_16K (1 << 13) #define ID2_PTFS_64K (1 << 14) #define PIDR2_ARCH_SHIFT 4 #define PIDR2_ARCH_MASK 0xf /* Perf Monitor registers */ #define ARM_SMMU_GNSR0_PMCNTENSET_0 0xc00 #define ARM_SMMU_GNSR0_PMCNTENCLR_0 0xc20 #define ARM_SMMU_GNSR0_PMINTENSET_0 0xc40 #define ARM_SMMU_GNSR0_PMINTENCLR_0 0xc60 #define ARM_SMMU_GNSR0_PMOVSCLR_0 0xc80 #define ARM_SMMU_GNSR0_PMOVSSET_0 0xcc0 #define ARM_SMMU_GNSR0_PMCFGR_0 0xe00 #define ARM_SMMU_GNSR0_PMCR_0 0xe04 #define ARM_SMMU_GNSR0_PMCEID0_0 0xe20 #define ARM_SMMU_GNSR0_PMAUTHSTATUS_0 0xfb8 #define ARM_SMMU_GNSR0_PMDEVTYPE_0 0xfcc #define ARM_SMMU_GNSR0_PMEVTYPER(n) (0x400 + ((n) << 2)) #define ARM_SMMU_GNSR0_PMEVCNTR(n) (0x0 + ((n) << 2)) #define ARM_SMMU_GNSR0_PMCGCR(n) (0x800 + ((n) << 2)) #define ARM_SMMU_GNSR0_PMCGSMR(n) (0xa00 + ((n) << 2)) /* Counter group registers */ #define PMCG_SIZE 32 /* Event Counter registers */ #define PMEV_SIZE 8 /* Global TLB invalidation */ #define ARM_SMMU_GR0_STLBIALL 0x60 #define ARM_SMMU_GR0_TLBIVMID 0x64 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 #define ARM_SMMU_GR0_TLBIALLH 0x6c #define ARM_SMMU_GR0_sTLBGSYNC 0x70 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 #define ARM_SMMU_GR0_nsTLBGSYNC 0x470 #define ARM_SMMU_GR0_nsTLBGSTATUS 0x474 #define sTLBGSTATUS_GSACTIVE (1 << 0) #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ /* Stream mapping registers */ #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) #define SMR_VALID (1 << 31) #define SMR_MASK_SHIFT 16 #define SMR_MASK_MASK 0x7f80 #define SMR_ID_SHIFT 0 #define SMR_ID_MASK 0x7f80 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) #define S2CR_CBNDX_SHIFT 0 #define S2CR_CBNDX_MASK 0xff #define S2CR_TYPE_SHIFT 16 #define S2CR_TYPE_MASK 0x3 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) /* Context bank attribute registers */ #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) #define CBAR_VMID_SHIFT 0 #define CBAR_VMID_MASK 0xff #define CBAR_S1_BPSHCFG_SHIFT 8 #define CBAR_S1_BPSHCFG_MASK 3 #define CBAR_S1_BPSHCFG_NSH 3 #define CBAR_S1_MEMATTR_SHIFT 12 #define CBAR_S1_MEMATTR_MASK 0xf #define CBAR_S1_MEMATTR_WB 0xf #define CBAR_TYPE_SHIFT 16 #define CBAR_TYPE_MASK 0x3 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) #define CBAR_IRPTNDX_SHIFT 24 #define CBAR_IRPTNDX_MASK 0xff #define ARM_SMMU_GR1_FRSYNRA(n) (0x400 + ((n) << 2)) #define FRSYNRA_STREAMID_MASK 0xffff #define FRSYNRA_STREAMID_SHIFT 0x0 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) #define CBA2R_RW64_32BIT (0 << 0) #define CBA2R_RW64_64BIT (1 << 0) /* Translation context bank */ #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 #define ARM_SMMU_CB_TTBR0_LO 0x20 #define ARM_SMMU_CB_TTBR0_HI 0x24 #define ARM_SMMU_CB_TTBR1_LO 0x28 #define ARM_SMMU_CB_TTBR1_HI 0x2c #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_CONTEXTIDR 0x34 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 #define ARM_SMMU_CB_FAR_LO 0x60 #define ARM_SMMU_CB_FAR_HI 0x64 #define ARM_SMMU_CB_FSYNR0 0x68 #define ARM_SMMU_CB_S1_TLBIASID 0x610 #define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIVAL 0x620 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 #define ARM_SMMU_CB_TLBSYNC 0x7f0 #define ARM_SMMU_CB_TLBSTATUS 0x7f4 #define SCTLR_S1_ASIDPNE (1 << 12) #define SCTLR_HUPCF (1 << 8) #define SCTLR_CFCFG (1 << 7) #define SCTLR_CFIE (1 << 6) #define SCTLR_CFRE (1 << 5) #define SCTLR_E (1 << 4) #define SCTLR_AFE (1 << 2) #define SCTLR_TRE (1 << 1) #define SCTLR_M (1 << 0) #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) #define RESUME_RETRY (0 << 0) #define RESUME_TERMINATE (1 << 0) #define TTBCR_EAE (1 << 31) #define TTBCR_PASIZE_SHIFT 16 #define TTBCR_PASIZE_MASK 0x7 #define TTBCR_TG0_4K (0 << 14) #define TTBCR_TG0_64K (1 << 14) #define TTBCR_SH0_SHIFT 12 #define TTBCR_SH0_MASK 0x3 #define TTBCR_SH_NS 0 #define TTBCR_SH_OS 2 #define TTBCR_SH_IS 3 #define TTBCR_ORGN0_SHIFT 10 #define TTBCR_IRGN0_SHIFT 8 #define TTBCR_RGN_MASK 0x3 #define TTBCR_RGN_NC 0 #define TTBCR_RGN_WBWA 1 #define TTBCR_RGN_WT 2 #define TTBCR_RGN_WB 3 #define TTBCR_SL0_SHIFT 6 #define TTBCR_SL0_MASK 0x3 #define TTBCR_SL0_LVL_2 0 #define TTBCR_SL0_LVL_1 1 #define TTBCR_T1SZ_SHIFT 16 #define TTBCR_T0SZ_SHIFT 0 #define TTBCR_SZ_MASK 0xf #define TTBCR2_SEP_SHIFT 15 #define TTBCR2_SEP_MASK 0x7 #define TTBCR2_PASIZE_SHIFT 0 #define TTBCR2_PASIZE_MASK 0x7 /* Common definitions for PASize and SEP fields */ #define TTBCR2_ADDR_32 0 #define TTBCR2_ADDR_36 1 #define TTBCR2_ADDR_40 2 #define TTBCR2_ADDR_42 3 #define TTBCR2_ADDR_44 4 #define TTBCR2_ADDR_48 5 #define TTBRn_HI_ASID_SHIFT 16 #define MAIR_ATTR_SHIFT(n) ((n) << 3) #define MAIR_ATTR_MASK 0xff #define MAIR_ATTR_DEVICE 0x04 #define MAIR_ATTR_NC 0x44 #define MAIR_ATTR_WBRWA 0xff #define MAIR_ATTR_IDX_NC 0 #define MAIR_ATTR_IDX_CACHE 1 #define MAIR_ATTR_IDX_DEV 2 #define FSR_MULTI (1 << 31) #define FSR_SS (1 << 30) #define FSR_UUT (1 << 8) #define FSR_ASF (1 << 7) #define FSR_TLBLKF (1 << 6) #define FSR_TLBMCF (1 << 5) #define FSR_EF (1 << 4) #define FSR_PF (1 << 3) #define FSR_AFF (1 << 2) #define FSR_TF (1 << 1) #define FSR_IGN (FSR_AFF | FSR_ASF | \ FSR_TLBMCF | FSR_TLBLKF) #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ FSR_EF | FSR_PF | FSR_TF | FSR_IGN) #define FSYNR0_WNR (1 << 4) #endif /* _ARM_SMMU_REGS_H */