/* * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __TEGRA210_MC_REG_H__ #define __TEGRA210_MC_REG_H__ #define MC_EMEM_ARB_MISC0 0xd8 #define MC_TIMING_CONTROL 0xfc #define MC_AHB_PTSA_MIN 0x4e0 #define MC_AUD_PTSA_MIN 0x54c #define MC_MLL_MPCORER_PTSA_RATE 0x44c #define MC_RING2_PTSA_RATE 0x440 #define MC_USBD_PTSA_RATE 0x530 #define MC_USBX_PTSA_MIN 0x528 #define MC_USBD_PTSA_MIN 0x534 #define MC_APB_PTSA_MAX 0x4f0 #define MC_JPG_PTSA_RATE 0x584 #define MC_DIS_PTSA_MIN 0x420 #define MC_AVP_PTSA_MAX 0x4fc #define MC_AVP_PTSA_RATE 0x4f4 #define MC_RING1_PTSA_MIN 0x480 #define MC_DIS_PTSA_MAX 0x424 #define MC_SD_PTSA_MAX 0x4d8 #define MC_MSE_PTSA_RATE 0x4c4 #define MC_VICPC_PTSA_MIN 0x558 #define MC_PCX_PTSA_MAX 0x4b4 #define MC_ISP_PTSA_RATE 0x4a0 #define MC_A9AVPPC_PTSA_MIN 0x48c #define MC_RING2_PTSA_MAX 0x448 #define MC_AUD_PTSA_RATE 0x548 #define MC_HOST_PTSA_MIN 0x51c #define MC_MLL_MPCORER_PTSA_MAX 0x454 #define MC_SD_PTSA_MIN 0x4d4 #define MC_RING1_PTSA_RATE 0x47c #define MC_JPG_PTSA_MIN 0x588 #define MC_HDAPC_PTSA_MIN 0x62c #define MC_AVP_PTSA_MIN 0x4f8 #define MC_JPG_PTSA_MAX 0x58c #define MC_VE_PTSA_MAX 0x43c #define MC_DFD_PTSA_MAX 0x63c #define MC_VICPC_PTSA_RATE 0x554 #define MC_GK_PTSA_MAX 0x544 #define MC_VICPC_PTSA_MAX 0x55c #define MC_SDM_PTSA_MAX 0x624 #define MC_SAX_PTSA_RATE 0x4b8 #define MC_PCX_PTSA_MIN 0x4b0 #define MC_APB_PTSA_MIN 0x4ec #define MC_GK2_PTSA_MIN 0x614 #define MC_PCX_PTSA_RATE 0x4ac #define MC_RING1_PTSA_MAX 0x484 #define MC_HDAPC_PTSA_RATE 0x628 #define MC_MLL_MPCORER_PTSA_MIN 0x450 #define MC_GK2_PTSA_MAX 0x618 #define MC_AUD_PTSA_MAX 0x550 #define MC_GK2_PTSA_RATE 0x610 #define MC_ISP_PTSA_MAX 0x4a8 #define MC_DISB_PTSA_RATE 0x428 #define MC_VE2_PTSA_MAX 0x49c #define MC_DFD_PTSA_MIN 0x638 #define MC_FTOP_PTSA_RATE 0x50c #define MC_A9AVPPC_PTSA_RATE 0x488 #define MC_VE2_PTSA_MIN 0x498 #define MC_USBX_PTSA_MAX 0x52c #define MC_DIS_PTSA_RATE 0x41c #define MC_USBD_PTSA_MAX 0x538 #define MC_A9AVPPC_PTSA_MAX 0x490 #define MC_USBX_PTSA_RATE 0x524 #define MC_FTOP_PTSA_MAX 0x514 #define MC_HDAPC_PTSA_MAX 0x630 #define MC_SD_PTSA_RATE 0x4d0 #define MC_DFD_PTSA_RATE 0x634 #define MC_FTOP_PTSA_MIN 0x510 #define MC_SDM_PTSA_RATE 0x61c #define MC_AHB_PTSA_RATE 0x4dc #define MC_SMMU_SMMU_PTSA_MAX 0x460 #define MC_RING2_PTSA_MIN 0x444 #define MC_SDM_PTSA_MIN 0x620 #define MC_APB_PTSA_RATE 0x4e8 #define MC_MSE_PTSA_MIN 0x4c8 #define MC_HOST_PTSA_RATE 0x518 #define MC_VE_PTSA_RATE 0x434 #define MC_AHB_PTSA_MAX 0x4e4 #define MC_SAX_PTSA_MIN 0x4bc #define MC_SMMU_SMMU_PTSA_MIN 0x45c #define MC_ISP_PTSA_MIN 0x4a4 #define MC_HOST_PTSA_MAX 0x520 #define MC_SAX_PTSA_MAX 0x4c0 #define MC_VE_PTSA_MIN 0x438 #define MC_GK_PTSA_MIN 0x540 #define MC_MSE_PTSA_MAX 0x4cc #define MC_DISB_PTSA_MAX 0x430 #define MC_DISB_PTSA_MIN 0x42c #define MC_SMMU_SMMU_PTSA_RATE 0x458 #define MC_VE2_PTSA_RATE 0x494 #define MC_GK_PTSA_RATE 0x53c #define MC_PTSA_GRANT_DECREMENT 0x960 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 #define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 #define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 #define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384 #define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc #define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 #define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 #define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 #define MC_LATENCY_ALLOWANCE_VIC_0 0x394 #define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 #define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 #define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc #define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 #define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 #define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 #define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698 #define MC_LATENCY_ALLOWANCE_DC_1 0x2ec #define MC_LATENCY_ALLOWANCE_APE_0 0x3dc #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0 #define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4 #define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 #define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 #define MC_LATENCY_ALLOWANCE_HC_1 0x314 #define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 #define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 #define MC_LATENCY_ALLOWANCE_PTC_0 0x34c #define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 #define MC_LATENCY_ALLOWANCE_VI2_0 0x398 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4 #define MC_LATENCY_ALLOWANCE_SATA_0 0x350 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690 #define MC_LATENCY_ALLOWANCE_HC_0 0x310 #define MC_LATENCY_ALLOWANCE_DC_3 0x3c8 #define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac #define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 #define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 #define MC_LATENCY_ALLOWANCE_HDA_0 0x318 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_HIGH_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_HIGH_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_HIGH_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_HIGH_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_HIGH_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_SHIFT 0 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_LOW_SHIFT) #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_SHIFT 16 #define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_MASK \ (0xff << MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_HIGH_SHIFT) #endif