/*
 * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _DT_BINDINGS_SOC_TEGRA210_POWERGATE_H
#define _DT_BINDINGS_SOC_TEGRA210_POWERGATE_H

#define TEGRA210_POWER_DOMAIN_CRAIL	0
#define TEGRA210_POWER_DOMAIN_VENC	2
#define TEGRA210_POWER_DOMAIN_PCIE	3
#define TEGRA210_POWER_DOMAIN_VDEC	4
#define TEGRA210_POWER_DOMAIN_L2	5
#define TEGRA210_POWER_DOMAIN_MPE	6
#define TEGRA210_POWER_DOMAIN_HEG	7
#define TEGRA210_POWER_DOMAIN_SATA	8
#define TEGRA210_POWER_DOMAIN_CPU1	9
#define TEGRA210_POWER_DOMAIN_CPU2	10
#define TEGRA210_POWER_DOMAIN_CPU3	11
#define TEGRA210_POWER_DOMAIN_CELP	12
#define TEGRA210_POWER_DOMAIN_3D1	13
#define TEGRA210_POWER_DOMAIN_CPU0	14
#define TEGRA210_POWER_DOMAIN_C0NC	15
#define TEGRA210_POWER_DOMAIN_C1NC	16
#define TEGRA210_POWER_DOMAIN_SOR	17
#define TEGRA210_POWER_DOMAIN_DISA	18
#define TEGRA210_POWER_DOMAIN_DISB	19
#define TEGRA210_POWER_DOMAIN_XUSBA	20
#define TEGRA210_POWER_DOMAIN_XUSBB	21
#define TEGRA210_POWER_DOMAIN_XUSBC	22
#define TEGRA210_POWER_DOMAIN_VIC	23
#define TEGRA210_POWER_DOMAIN_NVDEC	25
#define TEGRA210_POWER_DOMAIN_NVJPG	26
#define TEGRA210_POWER_DOMAIN_APE	27
#define TEGRA210_POWER_DOMAIN_VE2	29

#define TEGRA210_POWER_DOMAIN_MAX	30

#endif