NVIDIA Tegra SPE/AON aux CPU, with communication via the "IVC" IPC protocol.

AON is an aux CPU which communicates with CCPLEX over IVC.

The AON FW implements IVC, and uses HSP shared mailbox IRQs as part of IVC
notification. The AON FW expects AST regions 0/1 are already set up for the
AON to access SYSRAM and GSC carveout in DRAM. It configures the AST region
2 to point at DRAM IVC carveout upon receiving the carveout address and size
from CCPLEX.
 * Carveout address: SMMU IOVA of the IPC region
 * Slave address: Some hard coded location that SPE FW knows. Ex: 0x80000000

== AON top-level node ==

The AON core is represented by the top-level node.

Required properties:
- compatible: Should be "nvidia,tegra186-aon" for T18x.
- reg: Address entry of AON shared semaphore.
- nvidia,hsp-shared-mailbox: <HSP-phandle mailbox-number>
  * HSP is a set of HW synchronization primitives used in Tegra to allow
    multiple processors to share resources and communicate together.
  * hsp-shared-mailbox property points to shared mailbox pair used for
    IVC notification.
  * HSP-phandle points to the Tegra HSP platform device.
  * mailbox-number refers to the consumer side mailbox. The producer side
    mailbox is the other one in the same (even-odd) pair.
    Ex: consumer_mbox = 2; producer_mbox = (consumer_mbox ^ 1);
    A HSP irq notification allows a set of source agents in Tegra to request
    the attention of specified target agent. In general the agents are
    processors and irq is used as part of an IPC protocol notification.
  * For more HSP details, refer: ./tegra-hsp.txt.
- nvidia,ivc-carveout-base-ss: property holds the hsp shared semaphore index
  used to send the ivc carveout base address to the AON fw.
- nvidia,ivc-carveout-size-ss: property holds the hsp shared semaphore index
  used to send the ivc carveout size to the AON fw.
- nvidia,ivc-dbg-enable-ss: property holds the hsp shared semaphore index
  used to send the ivc channel id for debug to the AON fw.
- nvidia,ivc-notify-ss: property holds the hsp shared semaphore index used
  to send the ivc channels that are to be notified.

Mailbox controller properties:
- #mbox-cells
  Should be set to <1>.
The IVC channels are represented as mailbox channels.
Hence, this binding makes use of the mailbox binding at ../../mailbox/mailbox.txt.

SMMU properties:
- #stream-id-cells
  Should be set to <1>.
This property is used to configure the SMMU to SPE IVC carveout in DRAM.

== AON sub nodes ==

* ivc-channels
Contains a sub-node for each IVC channel implemented by the AON.
For IVC channel details, please refer: ./tegra-ivc-channel.txt

Possible example:

aon: aon@c160000 {
	compatible = "nvidia,tegra186-aon";
	reg = <0x0 0x0c1a0000 0x0 0x20000>; /* AON shared semaphore */
	#mbox-cells = <1>;
	#stream-id-cells = <1>;
	iommus = <&smmu TEGRA_SID_AON>;
	nvidia,hsp-shared-mailbox = <&aon_hsp 2>;
	nvidia,hsp-shared-mailbox-names = "ivc-pair";
	nvidia,ivc-carveout-base-ss = <0>;
	nvidia,ivc-carveout-size-ss = <1>;
	nvidia,ivc-notify-ss = <1>;
	nvidia,ivc-dbg-enable-ss = <0>;

	ivc-channels@80000000 {
		#address-cells = <1>;
		#size-cells = <0>;

		ivc_aon_echo@0 {
			reg = <0x0000>, <0x1000>;
			reg-names = "rx", "tx";
			nvidia,frame-count = <16>;
			nvidia,frame-size = <64>;
		};
		ivc_aon_aondbg@480 {
			reg = <0x0480>, <0x1480>;
			reg-names = "rx", "tx";
			nvidia,frame-count = <2>;
			nvidia,frame-size = <128>;
		};
	};
};