/* * DHD Bus Module for PCIE * * Portions of this code are copyright (c) 2017 Cypress Semiconductor Corporation * * Copyright (C) 1999-2017, Broadcom Corporation * * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the * following added to such license: * * As a special exception, the copyright holders of this software give you * permission to link this software with independent modules, and to copy and * distribute the resulting executable under terms of your choice, provided that * you also meet, for each linked independent module, the terms and conditions of * the license of that module. An independent module is a module which is not * derived from this software. The special exception does not apply to any * modifications of the software. * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * * * <> * * $Id: dhd_pcie.c 665937 2017-07-19 08:48:14Z $ */ /* include files */ #include #include #include #include #include #include #include #include #if defined(DHD_DEBUG) #include #endif /* defined(DHD_DEBUG) */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DHDTCPACK_SUPPRESS #include #endif /* DHDTCPACK_SUPPRESS */ #ifdef BCMEMBEDIMAGE #include BCMEMBEDIMAGE #endif /* BCMEMBEDIMAGE */ #ifdef PCIE_OOB #include "ftdi_sio_external.h" #endif /* PCIE_OOB */ #define CISTPL_BRCM_HNBU 0x80 #define HNBU_CUSTOM1 0x82 #define HNBU_CUSTOM2 0x83 #define CISTPL_NULL 0x00 #define CISTPL_END 0xff #define CISTPL_OFFSET 0xC0 #ifdef CUSTOMER_HW2 #define STARTBUSY_BIT_POLL_MAX_TIME 50 #endif /* CUSTOMER_HW2 */ #define MAX_WKLK_IDLE_CHECK 3 /* times wake_lock checked before deciding not to suspend */ #define ARMCR4REG_BANKIDX (0x40/sizeof(uint32)) #define ARMCR4REG_BANKPDA (0x4C/sizeof(uint32)) /* Temporary war to fix precommit till sync issue between trunk & precommit branch is resolved */ #if defined(SUPPORT_MULTIPLE_BOARD_REV) extern unsigned int system_rev; #endif /* SUPPORT_MULTIPLE_BOARD_REV */ /* DHD module parameter */ extern uint32 hw_module_variant; #define HW_MODULE_VARIANT_SHIFT 8 #define HW_MODULE_VARIANT_MASK 0xFF int dhd_dongle_memsize; int dhd_dongle_ramsize; static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size); #ifdef DHD_DEBUG static int dhdpcie_bus_readconsole(dhd_bus_t *bus); #endif /* DHD_DEBUG */ #if defined(DHD_FW_COREDUMP) struct dhd_bus *g_dhd_bus = NULL; static int dhdpcie_mem_dump(dhd_bus_t *bus); #endif /* DHD_FW_COREDUMP */ static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size); static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name, void *params, int plen, void *arg, int len, int val_size); static int dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 intval); static int dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus, uint32 len, uint32 srcdelay, uint32 destdelay); static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter); static int _dhdpcie_download_firmware(struct dhd_bus *bus); static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh); static int dhdpcie_bus_write_vars(dhd_bus_t *bus); static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus); static bool dhdpci_bus_read_frames(dhd_bus_t *bus); static int dhdpcie_readshared(dhd_bus_t *bus); static void dhdpcie_init_shared_addr(dhd_bus_t *bus); static bool dhdpcie_dongle_attach(dhd_bus_t *bus); static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size); static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag); static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh); static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len); static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data); static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data); static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data); static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data); static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data); static void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size); static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b); static int dhdpcie_sromotp_customvar(dhd_bus_t *bus, uint32 *customvar1, uint32 *customvar2); static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data); static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info); extern void dhd_dpc_kill(dhd_pub_t *dhdp); #ifdef BCM_AUTO_FWCRC extern int dhd_check_firmware_image(char* memptr, char *pfw_path); #endif #ifdef BCMEMBEDIMAGE static int dhdpcie_download_code_array(dhd_bus_t *bus); #endif /* BCMEMBEDIMAGE */ #ifdef EXYNOS_PCIE_DEBUG extern void exynos_pcie_register_dump(int ch_num); #endif /* EXYNOS_PCIE_DEBUG */ #define PCI_VENDOR_ID_BROADCOM 0x14e4 static void dhd_bus_set_device_wake(struct dhd_bus *bus, bool val); extern void wl_nddbg_wpp_log(const char *format, ...); #ifdef PCIE_OOB static void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus); #define DHD_DEFAULT_DOORBELL_TIMEOUT 200 /* ms */ static uint dhd_doorbell_timeout = DHD_DEFAULT_DOORBELL_TIMEOUT; #define HOST_WAKE 4 /* GPIO_0 (HOST_WAKE) - Output from WLAN */ #define DEVICE_WAKE 5 /* GPIO_1 (DEVICE_WAKE) - Input to WLAN */ #define BIT_WL_REG_ON 6 #define BIT_BT_REG_ON 7 int gpio_handle_val = 0; unsigned char gpio_port = 0; unsigned char gpio_direction = 0; #define OOB_PORT "ttyUSB0" #endif /* PCIE_OOB */ static bool dhdpcie_check_firmware_compatible(uint32 f_api_version, uint32 h_api_version); /* IOVar table */ enum { IOV_INTR = 1, IOV_MEMBYTES, IOV_MEMSIZE, IOV_SET_DOWNLOAD_STATE, IOV_DEVRESET, IOV_VARS, IOV_MSI_SIM, IOV_PCIE_LPBK, IOV_CC_NVMSHADOW, IOV_RAMSIZE, IOV_RAMSTART, IOV_SLEEP_ALLOWED, IOV_PCIE_DMAXFER, IOV_PCIE_SUSPEND, IOV_PCIEREG, IOV_PCIECFGREG, IOV_PCIECOREREG, IOV_PCIESERDESREG, IOV_BAR0_SECWIN_REG, IOV_SBREG, IOV_DONGLEISOLATION, IOV_LTRSLEEPON_UNLOOAD, IOV_METADATA_DBG, IOV_RX_METADATALEN, IOV_TX_METADATALEN, IOV_TXP_THRESHOLD, IOV_BUZZZ_DUMP, IOV_DUMP_RINGUPD_BLOCK, IOV_DMA_RINGINDICES, IOV_DB1_FOR_MB, IOV_FLOW_PRIO_MAP, #ifdef DHD_PCIE_RUNTIMEPM IOV_IDLETIME, #endif /* DHD_PCIE_RUNTIMEPM */ IOV_RXBOUND, IOV_TXBOUND, IOV_HANGREPORT, #ifdef PCIE_OOB IOV_OOB_BT_REG_ON, IOV_OOB_ENABLE #endif /* PCIE_OOB */ }; const bcm_iovar_t dhdpcie_iovars[] = { {"intr", IOV_INTR, 0, IOVT_BOOL, 0 }, {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int) }, {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0 }, {"dwnldstate", IOV_SET_DOWNLOAD_STATE, 0, IOVT_BOOL, 0 }, {"vars", IOV_VARS, 0, IOVT_BUFFER, 0 }, {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0 }, {"pcie_lpbk", IOV_PCIE_LPBK, 0, IOVT_UINT32, 0 }, {"cc_nvmshadow", IOV_CC_NVMSHADOW, 0, IOVT_BUFFER, 0 }, {"ramsize", IOV_RAMSIZE, 0, IOVT_UINT32, 0 }, {"ramstart", IOV_RAMSTART, 0, IOVT_UINT32, 0 }, {"pciereg", IOV_PCIEREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, {"pciecfgreg", IOV_PCIECFGREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, {"pciecorereg", IOV_PCIECOREREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, {"pcieserdesreg", IOV_PCIESERDESREG, 0, IOVT_BUFFER, 3 * sizeof(int32) }, {"bar0secwinreg", IOV_BAR0_SECWIN_REG, 0, IOVT_BUFFER, sizeof(sdreg_t) }, {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t) }, {"pcie_dmaxfer", IOV_PCIE_DMAXFER, 0, IOVT_BUFFER, 3 * sizeof(int32) }, {"pcie_suspend", IOV_PCIE_SUSPEND, 0, IOVT_UINT32, 0 }, #ifdef PCIE_OOB {"oob_bt_reg_on", IOV_OOB_BT_REG_ON, 0, IOVT_UINT32, 0 }, {"oob_enable", IOV_OOB_ENABLE, 0, IOVT_UINT32, 0 }, #endif /* PCIE_OOB */ {"sleep_allowed", IOV_SLEEP_ALLOWED, 0, IOVT_BOOL, 0 }, {"dngl_isolation", IOV_DONGLEISOLATION, 0, IOVT_UINT32, 0 }, {"ltrsleep_on_unload", IOV_LTRSLEEPON_UNLOOAD, 0, IOVT_UINT32, 0 }, {"dump_ringupdblk", IOV_DUMP_RINGUPD_BLOCK, 0, IOVT_BUFFER, 0 }, {"dma_ring_indices", IOV_DMA_RINGINDICES, 0, IOVT_UINT32, 0}, {"metadata_dbg", IOV_METADATA_DBG, 0, IOVT_BOOL, 0 }, {"rx_metadata_len", IOV_RX_METADATALEN, 0, IOVT_UINT32, 0 }, {"tx_metadata_len", IOV_TX_METADATALEN, 0, IOVT_UINT32, 0 }, {"db1_for_mb", IOV_DB1_FOR_MB, 0, IOVT_UINT32, 0 }, {"txp_thresh", IOV_TXP_THRESHOLD, 0, IOVT_UINT32, 0 }, {"buzzz_dump", IOV_BUZZZ_DUMP, 0, IOVT_UINT32, 0 }, {"flow_prio_map", IOV_FLOW_PRIO_MAP, 0, IOVT_UINT32, 0 }, #ifdef DHD_PCIE_RUNTIMEPM {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0 }, #endif /* DHD_PCIE_RUNTIMEPM */ {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0 }, {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0 }, {"fw_hang_report", IOV_HANGREPORT, 0, IOVT_BOOL, 0 }, {NULL, 0, 0, 0, 0 } }; #define MAX_READ_TIMEOUT 5 * 1000 * 1000 #ifndef DHD_RXBOUND #define DHD_RXBOUND 64 #endif #ifndef DHD_TXBOUND #define DHD_TXBOUND 64 #endif uint dhd_rxbound = DHD_RXBOUND; uint dhd_txbound = DHD_TXBOUND; /* Register/Unregister functions are called by the main DHD entry * point (e.g. module insertion) to link with the bus driver, in * order to look for or await the device. */ int dhd_bus_register(void) { DHD_TRACE(("%s: Enter\n", __FUNCTION__)); return dhdpcie_bus_register(); } void dhd_bus_unregister(void) { DHD_TRACE(("%s: Enter\n", __FUNCTION__)); dhdpcie_bus_unregister(); return; } /** returns a host virtual address */ uint32 * dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size) { return (uint32 *)REG_MAP(addr, size); } void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size) { REG_UNMAP((void*)(uintptr)addr); return; } /** * 'regs' is the host virtual address that maps to the start of the PCIe BAR0 window. The first 4096 * bytes in this window are mapped to the backplane address in the PCIEBAR0Window register. The * precondition is that the PCIEBAR0Window register 'points' at the PCIe core. * * 'tcm' is the *host* virtual address at which tcm is mapped. */ dhd_bus_t* dhdpcie_bus_attach(osl_t *osh, volatile char *regs, volatile char *tcm, void *pci_dev) { dhd_bus_t *bus; /* customvar1 and customvar2 are customer configurable CIS tuples in OTP. * In dual chip (PCIE) scenario, customvar2 is used as a hint to detect * the chip variants and load the right firmware and NVRAM */ /* Below vars are set to 0x0 as OTPed value can not take 0x0 */ uint32 customvar1 = 0x0; uint32 customvar2 = 0x0; uint32 otp_hw_module_variant = 0x0; DHD_TRACE(("%s: ENTER\n", __FUNCTION__)); do { if (!(bus = MALLOCZ(osh, sizeof(dhd_bus_t)))) { DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__)); break; } bus->regs = regs; bus->tcm = tcm; bus->osh = osh; /* Save pci_dev into dhd_bus, as it may be needed in dhd_attach */ bus->dev = (struct pci_dev *)pci_dev; dll_init(&bus->const_flowring); /* Attach pcie shared structure */ if (!(bus->pcie_sh = MALLOCZ(osh, sizeof(pciedev_shared_t)))) { DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__)); break; } /* dhd_common_init(osh); */ if (dhdpcie_dongle_attach(bus)) { DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__)); break; } if (!hw_module_variant) { /* For single wifi module */ goto enumerate_module; } /* read otp variables customvar1 and customvar2 */ if (dhdpcie_sromotp_customvar(bus, &customvar1, &customvar2)) { DHD_ERROR(("%s: dhdpcie_sromotp_customvar failed\n", __FUNCTION__)); break; } if (!customvar2) { DHD_ERROR(("%s: customvar2 is not OTPed, hw_module_variant=0x%x\n", __FUNCTION__, hw_module_variant)); goto enumerate_module; } /* customvar2=0xNNMMLLKK, LL is module variant */ otp_hw_module_variant = (customvar2 >> HW_MODULE_VARIANT_SHIFT) & HW_MODULE_VARIANT_MASK; if (hw_module_variant != otp_hw_module_variant) { DHD_ERROR(("%s: Not going to enumerate this module as " "hw_module_variant=0x%x and " "OTPed-module_variant=0x%x didn't match\n", __FUNCTION__, hw_module_variant, otp_hw_module_variant)); break; } DHD_ERROR(("%s: Going to enumerate this module as " "hw_module_variant=0x%x and " "OTPed-module_variant=0x%x match\n", __FUNCTION__, hw_module_variant, otp_hw_module_variant)); enumerate_module: /* software resources */ if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) { DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__)); break; } bus->dhd->busstate = DHD_BUS_DOWN; bus->db1_for_mb = TRUE; bus->dhd->hang_report = TRUE; bus->irq_registered = FALSE; bus->d3_ack_war_cnt = 0; DHD_TRACE(("%s: EXIT SUCCESS\n", __FUNCTION__)); #ifdef DHD_FW_COREDUMP g_dhd_bus = bus; #endif return bus; } while (0); DHD_TRACE(("%s: EXIT FAILURE\n", __FUNCTION__)); if (bus && bus->pcie_sh) { MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t)); } if (bus) { MFREE(osh, bus, sizeof(dhd_bus_t)); } return NULL; } uint dhd_bus_chip(struct dhd_bus *bus) { ASSERT(bus->sih != NULL); return bus->sih->chip; } uint dhd_bus_chiprev(struct dhd_bus *bus) { ASSERT(bus); ASSERT(bus->sih != NULL); return bus->sih->chiprev; } void * dhd_bus_pub(struct dhd_bus *bus) { return bus->dhd; } void * dhd_bus_sih(struct dhd_bus *bus) { return (void *)bus->sih; } void * dhd_bus_txq(struct dhd_bus *bus) { return &bus->txq; } /** Get Chip ID version */ uint dhd_bus_chip_id(dhd_pub_t *dhdp) { dhd_bus_t *bus = dhdp->bus; return bus->sih->chip; } /** Get Chip Rev ID version */ uint dhd_bus_chiprev_id(dhd_pub_t *dhdp) { dhd_bus_t *bus = dhdp->bus; return bus->sih->chiprev; } /** Get Chip Pkg ID version */ uint dhd_bus_chippkg_id(dhd_pub_t *dhdp) { dhd_bus_t *bus = dhdp->bus; return bus->sih->chippkg; } /** Read and clear intstatus. This should be called with interupts disabled or inside isr */ uint32 dhdpcie_bus_intstatus(dhd_bus_t *bus) { uint32 intstatus = 0; uint32 intmask = 0; if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) || (bus->sih->buscorerev == 2)) { intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus); intstatus &= I_MB; } else { /* this is a PCIE core register..not a config register... */ intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0); /* this is a PCIE core register..not a config register... */ intmask = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, 0, 0); /* * The fourth argument to si_corereg is the "mask" fields of the register to update * and the fifth field is the "value" to update. Now if we are interested in only * few fields of the "mask" bit map, we should not be writing back what we read * By doing so, we might clear/ack interrupts that are not handled yet. */ si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, bus->def_intmask, intstatus); intstatus &= intmask; /* Is device removed. intstatus & intmask read 0xffffffff */ if (intstatus == (uint32)-1) { DHD_ERROR(("%s: !!!!!!Device Removed or dead chip.\n", __FUNCTION__)); intstatus = 0; #ifdef CUSTOMER_HW4_DEBUG #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN; dhd_os_send_hang_message(bus->dhd); #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) && OEM_ANDROID */ #endif /* CUSTOMER_HW4_DEBUG */ } intstatus &= bus->def_intmask; } return intstatus; } /** * Name: dhdpcie_bus_isr * Parameters: * 1: IN int irq -- interrupt vector * 2: IN void *arg -- handle to private data structure * Return value: * Status (TRUE or FALSE) * * Description: * Interrupt Service routine checks for the status register, * disable interrupt and queue DPC if mail box interrupts are raised. */ int32 dhdpcie_bus_isr(dhd_bus_t *bus) { uint32 intstatus = 0; uint16 val = 0; do { DHD_TRACE(("%s: Enter\n", __FUNCTION__)); /* verify argument */ if (!bus) { DHD_ERROR(("%s : bus is null pointer, exit \n", __FUNCTION__)); break; } if (bus->dhd->dongle_reset) { break; } if (bus->dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: BUS is down, not processing the interrupt \r\n", __FUNCTION__)); break; } /* Wi-Fi chip registers to legacy PCIe interrupt, which shared by all root ports and end points. instatus filters out the irqs which are not from Wi-Fi chip, but when Wi-Fi chip is in D3hot instatus register is not accessible. So adding D3hot check before proceeding with isr routine */ pci_read_config_word(bus->dev, bus->dev->pm_cap + PCI_PM_CTRL, &val); if ((val & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot) { DHD_ERROR(("%s: chip is in D3 state, not processing the interrupt \r\n", __FUNCTION__)); break; } intstatus = dhdpcie_bus_intstatus(bus); /* Check if the interrupt is ours or not */ if (intstatus == 0) { break; } /* save the intstatus */ bus->intstatus = intstatus; /* Overall operation: * - Mask further interrupts * - Read/ack intstatus * - Take action based on bits and state * - Reenable interrupts (as per state) */ /* Count the interrupt call */ bus->intrcount++; /* read interrupt status register!! Status bits will be cleared in DPC !! */ bus->ipend = TRUE; dhdpcie_bus_intr_disable(bus); /* Disable interrupt!! */ bus->intdis = TRUE; #if defined(PCIE_ISR_THREAD) DHD_TRACE(("Calling dhd_bus_dpc() from %s\n", __FUNCTION__)); DHD_OS_WAKE_LOCK(bus->dhd); while (dhd_bus_dpc(bus)); DHD_OS_WAKE_UNLOCK(bus->dhd); #else bus->dpc_sched = TRUE; dhd_sched_dpc(bus->dhd); /* queue DPC now!! */ #endif /* defined(SDIO_ISR_THREAD) */ DHD_TRACE(("%s: Exit Success DPC Queued\n", __FUNCTION__)); return TRUE; } while (0); DHD_TRACE(("%s: Exit Failure\n", __FUNCTION__)); return FALSE; } #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY dhd_pub_t *link_recovery = NULL; #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */ static bool dhdpcie_dongle_attach(dhd_bus_t *bus) { osl_t *osh = bus->osh; void *regsva = (void*)bus->regs; uint16 devid = bus->cl_devid; uint32 val; sbpcieregs_t *sbpcieregs; DHD_TRACE(("%s: ENTER\n", __FUNCTION__)); #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY link_recovery = bus->dhd; #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */ bus->alp_only = TRUE; if (bus->sih != NULL) { DHD_INFO(("%s sih is not null\n", __FUNCTION__)); return 0; } /* Set bar0 window to si_enum_base */ dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE); /* Checking PCIe bus status with reading configuration space */ val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32)); if ((val & 0xFFFF) != VENDOR_BROADCOM) { DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__)); goto fail; } /* si_attach() will provide an SI handle and scan the backplane */ if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus, &bus->vars, &bus->varsz))) { DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__)); goto fail; } si_setcore(bus->sih, PCIE2_CORE_ID, 0); sbpcieregs = (sbpcieregs_t*)(bus->regs); /* WAR where the BAR1 window may not be sized properly */ W_REG(osh, &sbpcieregs->configaddr, 0x4e0); val = R_REG(osh, &sbpcieregs->configdata); W_REG(osh, &sbpcieregs->configdata, val); /* Get info on the ARM and SOCRAM cores... */ /* Should really be qualified by device id */ if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) || (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) || (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) || (si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { bus->armrev = si_corerev(bus->sih); } else { DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__)); goto fail; } if (si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) { if (!(bus->orig_ramsize = si_sysmem_size(bus->sih))) { DHD_ERROR(("%s: failed to find SYSMEM memory!\n", __FUNCTION__)); goto fail; } /* also populate base address */ bus->dongle_ram_base = CA7_4365_RAM_BASE; } else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { if (!(bus->orig_ramsize = si_socram_size(bus->sih))) { DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__)); goto fail; } } else { /* cr4 has a different way to find the RAM size from TCM's */ if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) { DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__)); goto fail; } /* also populate base address */ switch ((uint16)bus->sih->chip) { case BCM4339_CHIP_ID: case BCM4335_CHIP_ID: bus->dongle_ram_base = CR4_4335_RAM_BASE; break; case BCM4358_CHIP_ID: case BCM4356_CHIP_ID: case BCM4354_CHIP_ID: case BCM43567_CHIP_ID: case BCM43569_CHIP_ID: case BCM4350_CHIP_ID: case BCM43570_CHIP_ID: bus->dongle_ram_base = CR4_4350_RAM_BASE; break; case BCM4360_CHIP_ID: bus->dongle_ram_base = CR4_4360_RAM_BASE; break; CASE_BCM4345_CHIP: bus->dongle_ram_base = (bus->sih->chiprev < 6) /* changed at 4345C0 */ ? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE; break; CASE_BCM43602_CHIP: bus->dongle_ram_base = CR4_43602_RAM_BASE; break; case BCM4349_CHIP_GRPID: /* RAM base changed from 4349c0(revid=9) onwards */ bus->dongle_ram_base = ((bus->sih->chiprev < 9) ? CR4_4349_RAM_BASE : CR4_4349_RAM_BASE_FROM_REV_9); break; default: bus->dongle_ram_base = 0; DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n", __FUNCTION__, bus->dongle_ram_base)); } } bus->ramsize = bus->orig_ramsize; if (dhd_dongle_memsize) dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize); pr_info("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n", bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base); bus->srmemsize = si_socram_srmem_size(bus->sih); bus->def_intmask = PCIE_MB_D2H_MB_MASK | PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1; /* Set the poll and/or interrupt flags */ bus->intr = (bool)dhd_intr; bus->wait_for_d3_ack = 1; bus->suspended = FALSE; #ifdef PCIE_OOB gpio_handle_val = get_handle(OOB_PORT); if (gpio_handle_val < 0) { DHD_ERROR(("%s: Could not get GPIO handle.\n", __FUNCTION__)); ASSERT(FALSE); } gpio_direction = 0; ftdi_set_bitmode(gpio_handle_val, 0, BITMODE_BITBANG); /* Note BT core is also enabled here */ gpio_port = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE; gpio_write_port(gpio_handle_val, gpio_port); gpio_direction = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE; ftdi_set_bitmode(gpio_handle_val, gpio_direction, BITMODE_BITBANG); bus->oob_enabled = TRUE; /* drive the Device_Wake GPIO low on startup */ bus->device_wake_state = TRUE; dhd_bus_set_device_wake(bus, FALSE); dhd_bus_doorbell_timeout_reset(bus); #endif /* PCIE_OOB */ DHD_TRACE(("%s: EXIT: SUCCESS\n", __FUNCTION__)); return 0; fail: if (bus->sih != NULL) { si_detach(bus->sih); bus->sih = NULL; } DHD_TRACE(("%s: EXIT: FAILURE\n", __FUNCTION__)); return -1; } int dhpcie_bus_unmask_interrupt(dhd_bus_t *bus) { dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB); return 0; } int dhpcie_bus_mask_interrupt(dhd_bus_t *bus) { dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0); return 0; } void dhdpcie_bus_intr_enable(dhd_bus_t *bus) { DHD_TRACE(("enable interrupts\n")); if (bus && bus->sih && !bus->is_linkdown) { if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { dhpcie_bus_unmask_interrupt(bus); } else { si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, bus->def_intmask, bus->def_intmask); } } else { DHD_ERROR(("****** %s: failed ******\n", __FUNCTION__)); DHD_ERROR(("bus: %p sih: %p bus->is_linkdown %d\n", bus, bus ? bus->sih : NULL, bus ? bus->is_linkdown: -1)); } } void dhdpcie_bus_intr_disable(dhd_bus_t *bus) { DHD_TRACE(("%s Enter\n", __FUNCTION__)); if (bus && bus->sih && !bus->is_linkdown) { if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { dhpcie_bus_mask_interrupt(bus); } else { si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, bus->def_intmask, 0); } } else { DHD_ERROR(("****** %s: failed ******\n", __FUNCTION__)); DHD_ERROR(("bus: %p sih: %p bus->is_linkdown %d\n", bus, bus ? bus->sih : NULL, bus ? bus->is_linkdown: -1)); } DHD_TRACE(("%s Exit\n", __FUNCTION__)); } /* * dhdpcie_advertise_bus_cleanup advertises that clean up is under progress * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so * they will exit from there itself without marking dhd_bus_busy_state as BUSY. */ static void dhdpcie_advertise_bus_cleanup(dhd_pub_t *dhdp) { unsigned long flags; int timeleft; DHD_GENERAL_LOCK(dhdp, flags); dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS; DHD_GENERAL_UNLOCK(dhdp, flags); timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state); if (timeleft == 0) { DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n", __FUNCTION__, dhdp->dhd_bus_busy_state)); BUG_ON(1); } return; } static void dhdpcie_bus_remove_prep(dhd_bus_t *bus) { unsigned long flags; DHD_TRACE(("%s Enter\n", __FUNCTION__)); DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DOWN; DHD_GENERAL_UNLOCK(bus->dhd, flags); if (bus->sih == NULL) { return; } dhd_os_sdlock(bus->dhd); dhdpcie_bus_intr_disable(bus); if (!bus->dhd->dongle_isolation) { pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs)); } dhd_os_sdunlock(bus->dhd); DHD_TRACE(("%s Exit\n", __FUNCTION__)); } /** Detach and free everything */ void dhdpcie_bus_release(dhd_bus_t *bus) { bool dongle_isolation = FALSE; osl_t *osh = NULL; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); if (bus) { osh = bus->osh; ASSERT(osh); if (bus->dhd) { dhdpcie_advertise_bus_cleanup(bus->dhd); dongle_isolation = bus->dhd->dongle_isolation; dhdpcie_bus_remove_prep(bus); if (bus->intr) { dhdpcie_bus_intr_disable(bus); dhdpcie_free_irq(bus); } dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE); dhd_detach(bus->dhd); dhd_free(bus->dhd); bus->dhd = NULL; } /* unmap the regs and tcm here!! */ if (bus->regs) { dhdpcie_bus_reg_unmap(osh, (ulong)bus->regs, DONGLE_REG_MAP_SIZE); bus->regs = NULL; } if (bus->tcm) { dhdpcie_bus_reg_unmap(osh, (ulong)bus->tcm, DONGLE_TCM_MAP_SIZE); bus->tcm = NULL; } dhdpcie_bus_release_malloc(bus, osh); /* Detach pcie shared structure */ if (bus->pcie_sh) { MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t)); bus->pcie_sh = NULL; } #ifdef DHD_DEBUG if (bus->console.buf != NULL) MFREE(osh, bus->console.buf, bus->console.bufsize); #endif /* Finally free bus info */ MFREE(osh, bus, sizeof(dhd_bus_t)); } DHD_TRACE(("%s: Exit\n", __FUNCTION__)); } /* dhdpcie_bus_release */ void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag) { DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__, bus->dhd, bus->dhd->dongle_reset)); if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) { DHD_TRACE(("%s Exit\n", __FUNCTION__)); return; } if (bus->sih) { if (!dongle_isolation) pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs)); if (bus->ltrsleep_on_unload) { si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0); } if (bus->sih->buscorerev == 13) pcie_serdes_iddqdisable(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs)); if (bus->sih != NULL) { si_detach(bus->sih); bus->sih = NULL; } if (bus->vars && bus->varsz) MFREE(osh, bus->vars, bus->varsz); bus->vars = NULL; } DHD_TRACE(("%s Exit\n", __FUNCTION__)); } uint32 dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size) { uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size); return data; } /** 32 bit config write */ void dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data) { OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data); } void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data) { OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data); } void dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size) { int32 min_size = DONGLE_MIN_MEMSIZE; /* Restrict the memsize to user specified limit */ DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n", dhd_dongle_memsize, min_size)); if ((dhd_dongle_memsize > min_size) && (dhd_dongle_memsize < (int32)bus->orig_ramsize)) bus->ramsize = dhd_dongle_memsize; } void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh) { DHD_TRACE(("%s: Enter\n", __FUNCTION__)); if (bus->dhd && bus->dhd->dongle_reset) return; if (bus->vars && bus->varsz) { MFREE(osh, bus->vars, bus->varsz); bus->vars = NULL; } DHD_TRACE(("%s: Exit\n", __FUNCTION__)); return; } /** Stop bus module: clear pending frames, disable data flow */ void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) { uint32 status; unsigned long flags; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); if (!bus->dhd) return; if (bus->dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: already down by net_dev_reset\n", __FUNCTION__)); goto done; } DHD_DISABLE_RUNTIME_PM(bus->dhd); DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DOWN; DHD_GENERAL_UNLOCK(bus->dhd, flags); dhdpcie_bus_intr_disable(bus); status = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status); if (!dhd_download_fw_on_driverload) { dhd_dpc_kill(bus->dhd); } /* Clear rx control and wake any waiters */ dhd_os_set_ioctl_resp_timeout(IOCTL_DISABLE_TIMEOUT); dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_BUS_STOP); done: return; } /** Watchdog timer function */ bool dhd_bus_watchdog(dhd_pub_t *dhd) { unsigned long flags; #ifdef DHD_DEBUG dhd_bus_t *bus; bus = dhd->bus; DHD_GENERAL_LOCK(dhd, flags); if (dhd->busstate == DHD_BUS_DOWN || dhd->busstate == DHD_BUS_DOWN_IN_PROGRESS) { DHD_GENERAL_UNLOCK(dhd, flags); return FALSE; } dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD; DHD_GENERAL_UNLOCK(dhd, flags); #ifdef DHD_PCIE_RUNTIMEPM dhdpcie_runtime_bus_wake(dhd, TRUE, __builtin_return_address(0)); #endif /* DHD_PCIE_RUNTIMEPM */ /* Poll for console output periodically */ if (dhd->busstate == DHD_BUS_DATA && dhd_console_ms != 0) { bus->console.count += dhd_watchdog_ms; if (bus->console.count >= dhd_console_ms) { bus->console.count -= dhd_console_ms; /* Make sure backplane clock is on */ if (dhdpcie_bus_readconsole(bus) < 0) dhd_console_ms = 0; /* On error, stop trying */ } } #endif /* DHD_DEBUG */ #ifdef PCIE_OOB /* If haven't communicated with device for a while, deassert the Device_Wake GPIO */ if (dhd_doorbell_timeout != 0 && !(bus->dhd->busstate == DHD_BUS_SUSPEND) && dhd_timeout_expired(&bus->doorbell_timer)) { dhd_bus_set_device_wake(bus, FALSE); } #endif /* PCIE_OOB */ DHD_GENERAL_LOCK(dhd, flags); dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD; DHD_GENERAL_UNLOCK(dhd, flags); return TRUE; } /* dhd_bus_watchdog */ #define DEADBEEF_PATTERN 0xADDEADDE // "DeadDead" #define MEMCHECKINFO "/data/.memcheck.info" static int dhd_get_memcheck_info(void) { struct file *fp = NULL; uint32 mem_val = 0; int ret = 0; char *filepath = MEMCHECKINFO; fp = filp_open(filepath, O_RDONLY, 0); if (IS_ERR(fp)) { DHD_INFO(("[WIFI_SEC] %s: File [%s] doesn't exist\n", __FUNCTION__, filepath)); goto done; } else { #if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 13, 0)) ret = kernel_read(fp, (char *)&mem_val, 4, 0); #else ret = kernel_read(fp, 0, (char *)&mem_val, 4); #endif if (ret < 0) { DHD_ERROR(("[WIFI_SEC] %s: File read error, ret=%d\n", __FUNCTION__, ret)); filp_close(fp, NULL); goto done; } mem_val = bcm_atoi((char *)&mem_val); DHD_INFO(("[WIFI_SEC]%s: MEMCHECK ENABLED = %d\n", __FUNCTION__, mem_val)); filp_close(fp, NULL); } done: return mem_val; } static int dhdpcie_mem_check(struct dhd_bus *bus) { int bcmerror = BCME_OK; int offset = 0; int len = 0; uint8 *memblock = NULL, *memptr; int size = bus->ramsize; int i; uint32 memcheck_enabled; /* Read memcheck info from the file */ /* 0 : Disable */ /* 1 : "Dead Beef" pattern write */ /* 2 : "Dead Beef" pattern write and checking the pattern value */ memcheck_enabled = dhd_get_memcheck_info(); DHD_INFO(("%s: memcheck_enabled: %d \n", __FUNCTION__, memcheck_enabled)); if (memcheck_enabled == 0) { return bcmerror; } memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); if (memblock == NULL) { DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); goto err; } if ((ulong)memblock % DHD_SDALIGN) { memptr += (DHD_SDALIGN - ((ulong)memblock % DHD_SDALIGN)); } for (i = 0; i < MEMBLOCK; i = i + 4) { *(ulong*)(memptr + i) = DEADBEEF_PATTERN; } if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { if (offset == 0) { /* Add start of RAM address to the address given by user */ offset += bus->dongle_ram_base; } } /* Write "DeadBeef" pattern with MEMBLOCK size */ while (size) { len = MIN(MEMBLOCK, size); bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len); if (bcmerror) { DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", __FUNCTION__, bcmerror, MEMBLOCK, offset)); goto err; } if (memcheck_enabled == 2) { bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, (uint8 *)memptr, len); if (bcmerror) { DHD_ERROR(("%s: error %d on read %d membytes at 0x%08x\n", __FUNCTION__, bcmerror, MEMBLOCK, offset)); goto err; } else { for (i = 0; i < len; i = i+4) { if ((*(uint32*)(memptr + i)) != DEADBEEF_PATTERN) { DHD_ERROR(("%s: error on reading pattern at " "0x%08x\n", __FUNCTION__, (offset + i))); bcmerror = BCME_ERROR; goto err; } } } } offset += MEMBLOCK; size -= MEMBLOCK; } DHD_ERROR(("%s: Writing the Dead Beef pattern is Done \n", __FUNCTION__)); err: if (memblock) { MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); } return bcmerror; } /* Download firmware image and nvram image */ int dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, char *pfw_path, char *pnv_path) { int ret; bus->fw_path = pfw_path; bus->nv_path = pnv_path; DHD_INFO(("%s: firmware path=%s, nvram path=%s\n", __FUNCTION__, bus->fw_path, bus->nv_path)); dhdpcie_mem_check(bus); ret = dhdpcie_download_firmware(bus, osh); return ret; } static int dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh) { int ret = 0; #if defined(BCM_REQUEST_FW) uint chipid = bus->sih->chip; uint revid = bus->sih->chiprev; char fw_path[64] = "/lib/firmware/brcm/bcm"; /* path to firmware image */ char nv_path[64]; /* path to nvram vars file */ bus->fw_path = fw_path; bus->nv_path = nv_path; switch (chipid) { case BCM43570_CHIP_ID: bcmstrncat(fw_path, "43570", 5); switch (revid) { case 0: bcmstrncat(fw_path, "a0", 2); break; case 2: bcmstrncat(fw_path, "a2", 2); break; default: DHD_ERROR(("%s: revid is not found %x\n", __FUNCTION__, revid)); break; } break; default: DHD_ERROR(("%s: unsupported device %x\n", __FUNCTION__, chipid)); return 0; } /* load board specific nvram file */ snprintf(bus->nv_path, sizeof(nv_path), "%s.nvm", fw_path); /* load firmware */ snprintf(bus->fw_path, sizeof(fw_path), "%s-firmware.bin", fw_path); #endif /* BCM_REQUEST_FW */ DHD_OS_WAKE_LOCK(bus->dhd); ret = _dhdpcie_download_firmware(bus); DHD_OS_WAKE_UNLOCK(bus->dhd); return ret; } static int dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path) { int bcmerror = BCME_ERROR; int offset = 0; int len = 0; char *imgbuf = NULL; uint8 *memblock = NULL, *memptr; int offset_end = bus->ramsize; DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path)); memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); if (memblock == NULL) { DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); goto err; } #ifdef BCM_AUTO_FWCRC /* Firmware binary crc validation before downloading */ if (dhd_check_firmware_image(memptr, pfw_path)) { DHD_ERROR(("check image failed\n")); goto err; } #endif /* Should succeed in opening image if it is actually given through registry * entry or in module param. */ imgbuf = dhd_os_open_image(pfw_path); if (imgbuf == NULL) goto err; if ((uint32)(uintptr)memblock % DHD_SDALIGN) memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); DHD_INFO_HW4(("%s: dongle_ram_base: 0x%x ramsize: 0x%x tcm: %p\n", __FUNCTION__, bus->dongle_ram_base, bus->ramsize, bus->tcm)); /* Download image with MEMBLOCK size */ while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, imgbuf))) { if (len < 0) { DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len)); bcmerror = BCME_ERROR; goto err; } /* check if CR4/CA7 */ if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { /* if address is 0, store the reset instruction to be written in 0 */ if (offset == 0) { bus->resetinstr = *(((uint32*)memptr)); /* Add start of RAM address to the address given by user */ offset += bus->dongle_ram_base; offset_end += offset; } } bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len); if (bcmerror) { DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", __FUNCTION__, bcmerror, MEMBLOCK, offset)); goto err; } offset += MEMBLOCK; if (offset >= offset_end) { DHD_ERROR(("%s: invalid address access to %x (offset end: %x)\n", __FUNCTION__, offset, offset_end)); bcmerror = BCME_ERROR; goto err; } } err: if (memblock) MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); if (imgbuf) dhd_os_close_image(imgbuf); return bcmerror; } /* dhdpcie_download_code_file */ #ifdef CUSTOMER_HW4_DEBUG #define MIN_NVRAMVARS_SIZE 128 #endif /* CUSTOMER_HW4_DEBUG */ static int dhdpcie_download_nvram(struct dhd_bus *bus) { int bcmerror = BCME_ERROR; uint len; char * memblock = NULL; char *bufp; char *pnv_path; bool nvram_file_exists; bool nvram_uefi_exists = FALSE; bool local_alloc = FALSE; pnv_path = bus->nv_path; nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0')); /* First try UEFI */ len = MAX_NVRAMBUF_SIZE; dhd_get_download_buffer(bus->dhd, NULL, NVRAM, &memblock, &len); /* If UEFI empty, then read from file system */ if ((len == 0) || (memblock[0] == '\0')) { if (nvram_file_exists) { len = MAX_NVRAMBUF_SIZE; dhd_get_download_buffer(bus->dhd, pnv_path, NVRAM, &memblock, &len); if ((len <= 0 || len > MAX_NVRAMBUF_SIZE)) { goto err; } } else { /* For SROM OTP no external file or UEFI required */ bcmerror = BCME_OK; } } else { nvram_uefi_exists = TRUE; } DHD_INFO(("%s: dhd_get_download_buffer len %d\n", __FUNCTION__, len)); if (len > 0 && len <= MAX_NVRAMBUF_SIZE) { bufp = (char *) memblock; #ifdef CACHE_FW_IMAGES if (bus->processed_nvram_params_len) { len = bus->processed_nvram_params_len; } if (!bus->processed_nvram_params_len) { bufp[len] = 0; if (nvram_uefi_exists || nvram_file_exists) { len = process_nvram_vars(bufp, len); bus->processed_nvram_params_len = len; } } else #else { bufp[len] = 0; if (nvram_uefi_exists || nvram_file_exists) { len = process_nvram_vars(bufp, len); } } #endif /* CACHE_FW_IMAGES */ DHD_INFO(("%s: process_nvram_vars len %d\n", __FUNCTION__, len)); #ifdef CUSTOMER_HW4_DEBUG if (len < MIN_NVRAMVARS_SIZE) { DHD_ERROR(("%s: invalid nvram size in process_nvram_vars \n", __FUNCTION__)); bcmerror = BCME_ERROR; goto err; } #endif /* CUSTOMER_HW4_DEBUG */ if (len % 4) { len += 4 - (len % 4); } bufp += len; *bufp++ = 0; if (len) bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1); if (bcmerror) { DHD_ERROR(("%s: error downloading vars: %d\n", __FUNCTION__, bcmerror)); } } err: if (memblock) { if (local_alloc) { MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE); } else { dhd_free_download_buffer(bus->dhd, memblock, MAX_NVRAMBUF_SIZE); } } return bcmerror; } #ifdef BCMEMBEDIMAGE int dhdpcie_download_code_array(struct dhd_bus *bus) { int bcmerror = -1; int offset = 0; unsigned char *p_dlarray = NULL; unsigned int dlarray_size = 0; unsigned int downloded_len, remaining_len, len; char *p_dlimagename, *p_dlimagever, *p_dlimagedate; uint8 *memblock = NULL, *memptr; downloded_len = 0; remaining_len = 0; len = 0; p_dlarray = dlarray; dlarray_size = sizeof(dlarray); p_dlimagename = dlimagename; p_dlimagever = dlimagever; p_dlimagedate = dlimagedate; if ((p_dlarray == 0) || (dlarray_size == 0) ||(dlarray_size > bus->ramsize) || (p_dlimagename == 0) || (p_dlimagever == 0) || (p_dlimagedate == 0)) goto err; memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); if (memblock == NULL) { DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); goto err; } if ((uint32)(uintptr)memblock % DHD_SDALIGN) memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); while (downloded_len < dlarray_size) { remaining_len = dlarray_size - downloded_len; if (remaining_len >= MEMBLOCK) len = MEMBLOCK; else len = remaining_len; memcpy(memptr, (p_dlarray + downloded_len), len); /* check if CR4/CA7 */ if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) { /* if address is 0, store the reset instruction to be written in 0 */ if (offset == 0) { bus->resetinstr = *(((uint32*)memptr)); /* Add start of RAM address to the address given by user */ offset += bus->dongle_ram_base; } } bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len); downloded_len += len; if (bcmerror) { DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", __FUNCTION__, bcmerror, MEMBLOCK, offset)); goto err; } offset += MEMBLOCK; } #ifdef DHD_DEBUG /* Upload and compare the downloaded code */ { unsigned char *ularray = NULL; unsigned int uploded_len; uploded_len = 0; bcmerror = -1; ularray = MALLOC(bus->dhd->osh, dlarray_size); if (ularray == NULL) goto upload_err; /* Upload image to verify downloaded contents. */ offset = bus->dongle_ram_base; memset(ularray, 0xaa, dlarray_size); while (uploded_len < dlarray_size) { remaining_len = dlarray_size - uploded_len; if (remaining_len >= MEMBLOCK) len = MEMBLOCK; else len = remaining_len; bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, (uint8 *)(ularray + uploded_len), len); if (bcmerror) { DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", __FUNCTION__, bcmerror, MEMBLOCK, offset)); goto upload_err; } uploded_len += len; offset += MEMBLOCK; } if (memcmp(p_dlarray, ularray, dlarray_size)) { DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n", __FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate)); goto upload_err; } else DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n", __FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate)); upload_err: if (ularray) MFREE(bus->dhd->osh, ularray, dlarray_size); } #endif /* DHD_DEBUG */ err: if (memblock) MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); return bcmerror; } /* dhdpcie_download_code_array */ #endif /* BCMEMBEDIMAGE */ static int _dhdpcie_download_firmware(struct dhd_bus *bus) { int bcmerror = -1; bool embed = FALSE; /* download embedded firmware */ bool dlok = FALSE; /* download firmware succeeded */ /* Out immediately if no image to download */ if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) { #ifdef BCMEMBEDIMAGE embed = TRUE; #else DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__)); return 0; #endif } /* Keep arm in reset */ if (dhdpcie_bus_download_state(bus, TRUE)) { DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__)); goto err; } /* External image takes precedence if specified */ if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) { if (dhdpcie_download_code_file(bus, bus->fw_path)) { DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__)); #ifdef BCMEMBEDIMAGE embed = TRUE; #else goto err; #endif } else { embed = FALSE; dlok = TRUE; } } #ifdef BCMEMBEDIMAGE if (embed) { if (dhdpcie_download_code_array(bus)) { DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__)); goto err; } else { dlok = TRUE; } } #else BCM_REFERENCE(embed); #endif if (!dlok) { DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__)); goto err; } /* EXAMPLE: nvram_array */ /* If a valid nvram_arry is specified as above, it can be passed down to dongle */ /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */ /* External nvram takes precedence if specified */ if (dhdpcie_download_nvram(bus)) { DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__)); goto err; } /* Take arm out of reset */ if (dhdpcie_bus_download_state(bus, FALSE)) { DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__)); goto err; } bcmerror = 0; err: return bcmerror; } /* _dhdpcie_download_firmware */ #define CONSOLE_LINE_MAX 192 #ifdef DHD_DEBUG static int dhdpcie_bus_readconsole(dhd_bus_t *bus) { dhd_console_t *c = &bus->console; uint8 line[CONSOLE_LINE_MAX], ch; uint32 n, idx, addr; int rv; /* Don't do anything until FWREADY updates console address */ if (bus->console_addr == 0) return -1; /* Read console log struct */ addr = bus->console_addr + OFFSETOF(hnd_cons_t, log); if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0) return rv; /* Allocate console buffer (one time only) */ if (c->buf == NULL) { c->bufsize = ltoh32(c->log.buf_size); if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL) return BCME_NOMEM; } idx = ltoh32(c->log.idx); /* Protect against corrupt value */ if (idx > c->bufsize) return BCME_ERROR; /* Skip reading the console buffer if the index pointer has not moved */ if (idx == c->last) return BCME_OK; /* Read the console buffer */ addr = ltoh32(c->log.buf); if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0) return rv; while (c->last != idx) { for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { if (c->last == idx) { /* This would output a partial line. Instead, back up * the buffer pointer and output this line next time around. */ if (c->last >= n) c->last -= n; else c->last = c->bufsize - n; goto break2; } ch = c->buf[c->last]; c->last = (c->last + 1) % c->bufsize; if (ch == '\n') break; line[n] = ch; } if (n > 0) { if (line[n - 1] == '\r') n--; line[n] = 0; printf("CONSOLE: %s\n", line); } } break2: return BCME_OK; } /* dhdpcie_bus_readconsole */ #endif /* DHD_DEBUG */ static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size) { int bcmerror = 0; uint msize = 512; char *mbuffer = NULL; char *console_buffer = NULL; uint maxstrlen = 256; char *str = NULL; trap_t tr; pciedev_shared_t *pciedev_shared = bus->pcie_sh; struct bcmstrbuf strbuf; uint32 console_ptr, console_size, console_index; uint8 line[CONSOLE_LINE_MAX], ch; uint32 n, i, addr; int rv; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); if (DHD_NOCHECKDIED_ON()) { return 0; } if (data == NULL) { /* * Called after a rx ctrl timeout. "data" is NULL. * allocate memory to trace the trap or assert. */ size = msize; mbuffer = data = MALLOC(bus->dhd->osh, msize); if (mbuffer == NULL) { DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize)); bcmerror = BCME_NOMEM; goto done; } } if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) { DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen)); bcmerror = BCME_NOMEM; goto done; } if ((bcmerror = dhdpcie_readshared(bus)) < 0) { goto done; } bcm_binit(&strbuf, data, size); bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n", pciedev_shared->msgtrace_addr, pciedev_shared->console_addr); if ((pciedev_shared->flags & PCIE_SHARED_ASSERT_BUILT) == 0) { /* NOTE: Misspelled assert is intentional - DO NOT FIX. * (Avoids conflict with real asserts for programmatic parsing of output.) */ bcm_bprintf(&strbuf, "Assrt not built in dongle\n"); } if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) { /* NOTE: Misspelled assert is intentional - DO NOT FIX. * (Avoids conflict with real asserts for programmatic parsing of output.) */ bcm_bprintf(&strbuf, "No trap%s in dongle", (bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT) ?"/assrt" :""); } else { if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) { /* Download assert */ bcm_bprintf(&strbuf, "Dongle assert"); if (bus->pcie_sh->assert_exp_addr != 0) { str[0] = '\0'; if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, bus->pcie_sh->assert_exp_addr, (uint8 *)str, maxstrlen)) < 0) { goto done; } str[maxstrlen - 1] = '\0'; bcm_bprintf(&strbuf, " expr \"%s\"", str); } if (bus->pcie_sh->assert_file_addr != 0) { str[0] = '\0'; if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, bus->pcie_sh->assert_file_addr, (uint8 *)str, maxstrlen)) < 0) { goto done; } str[maxstrlen - 1] = '\0'; bcm_bprintf(&strbuf, " file \"%s\"", str); } bcm_bprintf(&strbuf, " line %d ", bus->pcie_sh->assert_line); } if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) { bus->dhd->dongle_trap_occured = TRUE; if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, bus->pcie_sh->trap_addr, (uint8*)&tr, sizeof(trap_t))) < 0) { goto done; } bcm_bprintf(&strbuf, "\nTRAP type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x," " lp 0x%x, rpc 0x%x" "\nTrap offset 0x%x, r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, " "r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n", ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr), ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc), ltoh32(bus->pcie_sh->trap_addr), ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3), ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7)); addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log); if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&console_ptr, sizeof(console_ptr))) < 0) { goto printbuf; } addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size); if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&console_size, sizeof(console_size))) < 0) { goto printbuf; } addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx); if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&console_index, sizeof(console_index))) < 0) { goto printbuf; } console_ptr = ltoh32(console_ptr); console_size = ltoh32(console_size); console_index = ltoh32(console_index); if (console_size > CONSOLE_BUFFER_MAX || !(console_buffer = MALLOC(bus->dhd->osh, console_size))) { goto printbuf; } if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr, (uint8 *)console_buffer, console_size)) < 0) { goto printbuf; } for (i = 0, n = 0; i < console_size; i += n + 1) { for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { ch = console_buffer[(console_index + i + n) % console_size]; if (ch == '\n') break; line[n] = ch; } if (n > 0) { if (line[n - 1] == '\r') n--; line[n] = 0; /* Don't use DHD_ERROR macro since we print * a lot of information quickly. The macro * will truncate a lot of the printfs */ printf("CONSOLE: %s\n", line); } } } } printbuf: if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) { printf("%s: %s\n", __FUNCTION__, strbuf.origbuf); /* wake up IOCTL wait event */ dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_TRAP); #if defined(DHD_FW_COREDUMP) /* save core dump or write to a file */ if (bus->dhd->memdump_enabled) { bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP; dhdpcie_mem_dump(bus); } #endif /* DHD_FW_COREDUMP */ } done: if (mbuffer) MFREE(bus->dhd->osh, mbuffer, msize); if (str) MFREE(bus->dhd->osh, str, maxstrlen); if (console_buffer) MFREE(bus->dhd->osh, console_buffer, console_size); return bcmerror; } /* dhdpcie_checkdied */ /* Custom copy of dhdpcie_mem_dump() that can be called at interrupt level */ void dhdpcie_mem_dump_bugcheck(dhd_bus_t *bus, uint8 *buf) { int ret = 0; int size; /* Full mem size */ int start; /* Start address */ int read_size = 0; /* Read size of each iteration */ uint8 *databuf = buf; if (bus == NULL) { return; } start = bus->dongle_ram_base; /* Get full mem size */ size = bus->ramsize; /* Read mem content */ while (size) { read_size = MIN(MEMBLOCK, size); if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) { return; } /* Decrement size and increment start address */ size -= read_size; start += read_size; databuf += read_size; } bus->dhd->soc_ram = buf; bus->dhd->soc_ram_length = bus->ramsize; return; } #if defined(DHD_FW_COREDUMP) static int dhdpcie_mem_dump(dhd_bus_t *bus) { int ret = 0; int size; /* Full mem size */ int start = bus->dongle_ram_base; /* Start address */ int read_size = 0; /* Read size of each iteration */ uint8 *buf = NULL, *databuf = NULL; #ifdef EXYNOS_PCIE_DEBUG exynos_pcie_register_dump(1); #endif /* EXYNOS_PCIE_DEBUG */ #ifdef SUPPORT_LINKDOWN_RECOVERY if (bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down so skip\n", __FUNCTION__)); return BCME_ERROR; } #endif /* SUPPORT_LINKDOWN_RECOVERY */ /* Get full mem size */ size = bus->ramsize; #if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP) buf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_MEMDUMP_BUF, size); bzero(buf, size); #else buf = MALLOC(bus->dhd->osh, size); #endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */ if (!buf) { DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size)); return BCME_ERROR; } /* Read mem content */ DHD_TRACE_HW4(("Dump dongle memory")); databuf = buf; while (size) { read_size = MIN(MEMBLOCK, size); if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) { DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret)); if (buf) { MFREE(bus->dhd->osh, buf, size); } bus->dhd->memdump_success = FALSE; return BCME_ERROR; } DHD_TRACE((".")); /* Decrement size and increment start address */ size -= read_size; start += read_size; databuf += read_size; } bus->dhd->memdump_success = TRUE; DHD_TRACE_HW4(("%s FUNC: Copy fw image to the embedded buffer \n", __FUNCTION__)); dhd_save_fwdump(bus->dhd, buf, bus->ramsize); dhd_schedule_memdump(bus->dhd, buf, bus->ramsize); return ret; } int dhd_bus_mem_dump(dhd_pub_t *dhdp) { dhd_bus_t *bus = dhdp->bus; if (bus->suspended) { DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__)); return 0; } return dhdpcie_mem_dump(bus); } #ifdef BCMDHDX int dhdx_dongle_mem_dump() { if (!g_dhd_bus) { DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__)); return -ENODEV; } if (g_dhd_bus->suspended) { DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__)); return 0; } g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON; g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS; return dhdpcie_mem_dump(g_dhd_bus); } EXPORT_SYMBOL(dhdx_dongle_mem_dump); #else int dhd_dongle_mem_dump() { if (!g_dhd_bus) { DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__)); return -ENODEV; } if (g_dhd_bus->suspended) { DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__)); return 0; } g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON; g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS; return dhdpcie_mem_dump(g_dhd_bus); } EXPORT_SYMBOL(dhd_dongle_mem_dump); #endif /* BCMDHDX */ #endif /* DHD_FW_COREDUMP */ int dhd_socram_dump(dhd_bus_t *bus) { #if defined(DHD_FW_COREDUMP) return (dhdpcie_mem_dump(bus)); #else return -1; #endif } /** * Transfers bytes from host to dongle using pio mode. * Parameter 'address' is a backplane address. */ static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size) { uint dsize; int detect_endian_flag = 0x01; bool little_endian; if (write && bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); return BCME_ERROR; } /* Detect endianness. */ little_endian = *(char *)&detect_endian_flag; /* In remap mode, adjust address beyond socram and redirect * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize * is not backplane accessible */ /* Determine initial transfer parameters */ dsize = sizeof(uint64); /* Do the transfer(s) */ if (write) { while (size) { if (size >= sizeof(uint64) && little_endian && #ifdef CONFIG_64BIT !(address % 8) && #endif /* CONFIG_64BIT */ 1) { dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data)); } else { dsize = sizeof(uint8); dhdpcie_bus_wtcm8(bus, address, *data); } /* Adjust for next transfer (if any) */ if ((size -= dsize)) { data += dsize; address += dsize; } } } else { while (size) { if (size >= sizeof(uint64) && little_endian && #ifdef CONFIG_64BIT !(address % 8) && #endif /* CONFIG_64BIT */ 1) { *(uint64 *)data = dhdpcie_bus_rtcm64(bus, address); } else { dsize = sizeof(uint8); *data = dhdpcie_bus_rtcm8(bus, address); } /* Adjust for next transfer (if any) */ if ((size -= dsize) > 0) { data += dsize; address += dsize; } } } return BCME_OK; } /* dhdpcie_bus_membytes */ /** * Transfers one transmit (ethernet) packet that was queued in the (flow controlled) flow ring queue * to the (non flow controlled) flow ring. */ int BCMFASTPATH dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs) { flow_ring_node_t *flow_ring_node; int ret = BCME_OK; #ifdef DHD_LOSSLESS_ROAMING dhd_pub_t *dhdp = bus->dhd; #endif DHD_INFO(("%s: flow_id is %d\n", __FUNCTION__, flow_id)); /* ASSERT on flow_id */ if (flow_id >= bus->max_sub_queues) { DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__, flow_id, bus->max_sub_queues)); return 0; } flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id); #ifdef DHD_LOSSLESS_ROAMING if ((dhdp->dequeue_prec_map & (1 << flow_ring_node->flow_info.tid)) == 0) { DHD_INFO(("%s: tid %d is not in precedence map. block scheduling\n", __FUNCTION__, flow_ring_node->flow_info.tid)); return BCME_OK; } #endif /* DHD_LOSSLESS_ROAMING */ { unsigned long flags; void *txp = NULL; flow_queue_t *queue; #ifdef DHD_LOSSLESS_ROAMING struct ether_header *eh; uint8 *pktdata; #endif /* DHD_LOSSLESS_ROAMING */ queue = &flow_ring_node->queue; /* queue associated with flow ring */ DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) { DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); return BCME_NOTREADY; } while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { PKTORPHAN(txp); /* * Modifying the packet length caused P2P cert failures. * Specifically on test cases where a packet of size 52 bytes * was injected, the sniffer capture showed 62 bytes because of * which the cert tests failed. So making the below change * only Router specific. */ #ifdef DHDTCPACK_SUPPRESS if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_HOLD) { ret = dhd_tcpack_check_xmit(bus->dhd, txp); if (ret != BCME_OK) { DHD_ERROR(("%s: dhd_tcpack_check_xmit() error.\n", __FUNCTION__)); } } #endif /* DHDTCPACK_SUPPRESS */ #ifdef DHD_LOSSLESS_ROAMING pktdata = (uint8 *)PKTDATA(OSH_NULL, txp); eh = (struct ether_header *) pktdata; if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) { uint8 prio = (uint8)PKTPRIO(txp); /* Restore to original priority for 802.1X packet */ if (prio == PRIO_8021D_NC) { PKTSETPRIO(txp, dhdp->prio_8021x); } } #endif /* DHD_LOSSLESS_ROAMING */ /* Attempt to transfer packet over flow ring */ ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex); if (ret != BCME_OK) { /* may not have resources in flow ring */ DHD_INFO(("%s: Reinserrt %d\n", __FUNCTION__, ret)); dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE); /* reinsert at head */ dhd_flow_queue_reinsert(bus->dhd, queue, txp); DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); /* If we are able to requeue back, return success */ return BCME_OK; } } dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE); DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); } return ret; } /* dhd_bus_schedule_queue */ /** Sends an (ethernet) data frame (in 'txp') to the dongle. Callee disposes of txp. */ int BCMFASTPATH dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx) { uint16 flowid; flow_queue_t *queue; flow_ring_node_t *flow_ring_node; unsigned long flags; int ret = BCME_OK; void *txp_pend = NULL; if (!bus->dhd->flowid_allocator) { DHD_ERROR(("%s: Flow ring not intited yet \n", __FUNCTION__)); goto toss; } flowid = DHD_PKT_GET_FLOWID(txp); flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); DHD_TRACE(("%s: pkt flowid %d, status %d active %d\n", __FUNCTION__, flowid, flow_ring_node->status, flow_ring_node->active)); DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); if ((flowid >= bus->dhd->num_flow_rings) || (!flow_ring_node->active) || (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) || (flow_ring_node->status == FLOW_RING_STATUS_STA_FREEING)) { DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); DHD_INFO(("%s: Dropping pkt flowid %d, status %d active %d\n", __FUNCTION__, flowid, flow_ring_node->status, flow_ring_node->active)); ret = BCME_ERROR; goto toss; } queue = &flow_ring_node->queue; /* queue associated with flow ring */ if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK) { txp_pend = txp; } DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); if (flow_ring_node->status) { DHD_INFO(("%s: Enq pkt flowid %d, status %d active %d\n", __FUNCTION__, flowid, flow_ring_node->status, flow_ring_node->active)); if (txp_pend) { txp = txp_pend; goto toss; } return BCME_OK; } ret = dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */ /* If we have anything pending, try to push into q */ if (txp_pend) { DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) { DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); txp = txp_pend; goto toss; } DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); } return ret; toss: DHD_INFO(("%s: Toss %d\n", __FUNCTION__, ret)); PKTCFREE(bus->dhd->osh, txp, TRUE); return ret; } /* dhd_bus_txdata */ void dhd_bus_stop_queue(struct dhd_bus *bus) { dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON); bus->bus_flowctrl = TRUE; } void dhd_bus_start_queue(struct dhd_bus *bus) { dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF); bus->bus_flowctrl = TRUE; } #if defined(DHD_DEBUG) /* Device console input function */ int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen) { dhd_bus_t *bus = dhd->bus; uint32 addr, val; int rv; /* Address could be zero if CONSOLE := 0 in dongle Makefile */ if (bus->console_addr == 0) return BCME_UNSUPPORTED; /* Don't allow input if dongle is in reset */ if (bus->dhd->dongle_reset) { dhd_os_sdunlock(bus->dhd); return BCME_NOTREADY; } /* Zero cbuf_index */ addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx); val = htol32(0); if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) goto done; /* Write message into cbuf */ addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf); if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0) goto done; /* Write length into vcons_in */ addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in); val = htol32(msglen); if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) goto done; /* generate an interrupt to dongle to indicate that it needs to process cons command */ dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT); done: return rv; } /* dhd_bus_console_in */ #endif /* defined(DHD_DEBUG) */ /** * Called on frame reception, the frame was received from the dongle on interface 'ifidx' and is * contained in 'pkt'. Processes rx frame, forwards up the layer to netif. */ void BCMFASTPATH dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count) { dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0); } /** 'offset' is a backplane address */ void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data) { *(volatile uint8 *)(bus->tcm + offset) = (uint8)data; } uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset) { volatile uint8 data; data = *(volatile uint8 *)(bus->tcm + offset); return data; } void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data) { *(volatile uint32 *)(bus->tcm + offset) = (uint32)data; } void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data) { *(volatile uint16 *)(bus->tcm + offset) = (uint16)data; } void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data) { *(volatile uint64 *)(bus->tcm + offset) = (uint64)data; } uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset) { volatile uint16 data; data = *(volatile uint16 *)(bus->tcm + offset); return data; } uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset) { volatile uint32 data; data = *(volatile uint32 *)(bus->tcm + offset); return data; } uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset) { volatile uint64 data; data = *(volatile uint64 *)(bus->tcm + offset); return data; } /** A snippet of dongle memory is shared between host and dongle */ void dhd_bus_cmn_writeshared(dhd_bus_t *bus, void *data, uint32 len, uint8 type, uint16 ringid) { uint64 long_data; ulong tcm_offset; DHD_INFO(("%s: writing to dongle type %d len %d\n", __FUNCTION__, type, len)); if (bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); return; } switch (type) { case D2H_DMA_SCRATCH_BUF: { pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr; long_data = HTOL64(*(uint64 *)data); tcm_offset = (ulong)&(sh->host_dma_scratch_buffer); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); prhex(__FUNCTION__, data, len); break; } case D2H_DMA_SCRATCH_BUF_LEN: { pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr; tcm_offset = (ulong)&(sh->host_dma_scratch_buffer_len); dhdpcie_bus_wtcm32(bus, tcm_offset, (uint32) HTOL32(*(uint32 *)data)); prhex(__FUNCTION__, data, len); break; } case H2D_DMA_INDX_WR_BUF: { pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh; long_data = HTOL64(*(uint64 *)data); tcm_offset = (ulong)shmem->rings_info_ptr; tcm_offset += OFFSETOF(ring_info_t, h2d_w_idx_hostaddr); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); prhex(__FUNCTION__, data, len); break; } case H2D_DMA_INDX_RD_BUF: { pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh; long_data = HTOL64(*(uint64 *)data); tcm_offset = (ulong)shmem->rings_info_ptr; tcm_offset += OFFSETOF(ring_info_t, h2d_r_idx_hostaddr); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); prhex(__FUNCTION__, data, len); break; } case D2H_DMA_INDX_WR_BUF: { pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh; long_data = HTOL64(*(uint64 *)data); tcm_offset = (ulong)shmem->rings_info_ptr; tcm_offset += OFFSETOF(ring_info_t, d2h_w_idx_hostaddr); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); prhex(__FUNCTION__, data, len); break; } case D2H_DMA_INDX_RD_BUF: { pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh; long_data = HTOL64(*(uint64 *)data); tcm_offset = (ulong)shmem->rings_info_ptr; tcm_offset += OFFSETOF(ring_info_t, d2h_r_idx_hostaddr); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); prhex(__FUNCTION__, data, len); break; } case RING_ITEM_LEN: tcm_offset = bus->ring_sh[ringid].ring_mem_addr; tcm_offset += OFFSETOF(ring_mem_t, len_items); dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); break; case RING_MAX_ITEMS: tcm_offset = bus->ring_sh[ringid].ring_mem_addr; tcm_offset += OFFSETOF(ring_mem_t, max_item); dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); break; case RING_BUF_ADDR: long_data = HTOL64(*(uint64 *)data); tcm_offset = bus->ring_sh[ringid].ring_mem_addr; tcm_offset += OFFSETOF(ring_mem_t, base_addr); dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8 *) &long_data, len); prhex(__FUNCTION__, data, len); break; case RING_WR_UPD: tcm_offset = bus->ring_sh[ringid].ring_state_w; dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); break; case RING_RD_UPD: tcm_offset = bus->ring_sh[ringid].ring_state_r; dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); break; case D2H_MB_DATA: dhdpcie_bus_wtcm32(bus, bus->d2h_mb_data_ptr_addr, (uint32) HTOL32(*(uint32 *)data)); break; case H2D_MB_DATA: dhdpcie_bus_wtcm32(bus, bus->h2d_mb_data_ptr_addr, (uint32) HTOL32(*(uint32 *)data)); break; default: break; } } /* dhd_bus_cmn_writeshared */ /** A snippet of dongle memory is shared between host and dongle */ void dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid) { ulong tcm_offset; switch (type) { case RING_WR_UPD: tcm_offset = bus->ring_sh[ringid].ring_state_w; *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset)); break; case RING_RD_UPD: tcm_offset = bus->ring_sh[ringid].ring_state_r; *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset)); break; case TOTAL_LFRAG_PACKET_CNT: { pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr; *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, (ulong) &sh->total_lfrag_pkt_cnt)); break; } case H2D_MB_DATA: *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->h2d_mb_data_ptr_addr)); break; case D2H_MB_DATA: *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->d2h_mb_data_ptr_addr)); break; case MAX_HOST_RXBUFS: { pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr; *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, (ulong) &sh->max_host_rxbufs)); break; } default : break; } } uint32 dhd_bus_get_sharedflags(dhd_bus_t *bus) { return ((pciedev_shared_t*)bus->pcie_sh)->flags; } void dhd_bus_clearcounts(dhd_pub_t *dhdp) { } int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name, void *params, int plen, void *arg, int len, bool set) { dhd_bus_t *bus = dhdp->bus; const bcm_iovar_t *vi = NULL; int bcmerror = 0; int val_size; uint32 actionid; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); ASSERT(name); ASSERT(len >= 0); /* Get MUST have return space */ ASSERT(set || (arg && len)); /* Set does NOT take qualifiers */ ASSERT(!set || (!params && !plen)); DHD_INFO(("%s: %s %s, len %d plen %d\n", __FUNCTION__, name, (set ? "set" : "get"), len, plen)); /* Look up var locally; if not found pass to host driver */ if ((vi = bcm_iovar_lookup(dhdpcie_iovars, name)) == NULL) { goto exit; } /* set up 'params' pointer in case this is a set command so that * the convenience int and bool code can be common to set and get */ if (params == NULL) { params = arg; plen = len; } if (vi->type == IOVT_VOID) val_size = 0; else if (vi->type == IOVT_BUFFER) val_size = len; else /* all other types are integer sized */ val_size = sizeof(int); actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid); bcmerror = dhdpcie_bus_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size); exit: return bcmerror; } /* dhd_bus_iovar_op */ #ifdef BCM_BUZZZ #include int dhd_buzzz_dump_cntrs(char *p, uint32 *core, uint32 *log, const int num_counters) { int bytes = 0; uint32 ctr; uint32 curr[BCM_BUZZZ_COUNTERS_MAX], prev[BCM_BUZZZ_COUNTERS_MAX]; uint32 delta[BCM_BUZZZ_COUNTERS_MAX]; /* Compute elapsed counter values per counter event type */ for (ctr = 0U; ctr < num_counters; ctr++) { prev[ctr] = core[ctr]; curr[ctr] = *log++; core[ctr] = curr[ctr]; /* saved for next log */ if (curr[ctr] < prev[ctr]) delta[ctr] = curr[ctr] + (~0U - prev[ctr]); else delta[ctr] = (curr[ctr] - prev[ctr]); bytes += sprintf(p + bytes, "%12u ", delta[ctr]); } return bytes; } typedef union cm3_cnts { /* export this in bcm_buzzz.h */ uint32 u32; uint8 u8[4]; struct { uint8 cpicnt; uint8 exccnt; uint8 sleepcnt; uint8 lsucnt; }; } cm3_cnts_t; int dhd_bcm_buzzz_dump_cntrs6(char *p, uint32 *core, uint32 *log) { int bytes = 0; uint32 cyccnt, instrcnt; cm3_cnts_t cm3_cnts; uint8 foldcnt; { /* 32bit cyccnt */ uint32 curr, prev, delta; prev = core[0]; curr = *log++; core[0] = curr; if (curr < prev) delta = curr + (~0U - prev); else delta = (curr - prev); bytes += sprintf(p + bytes, "%12u ", delta); cyccnt = delta; } { /* Extract the 4 cnts: cpi, exc, sleep and lsu */ int i; uint8 max8 = ~0; cm3_cnts_t curr, prev, delta; prev.u32 = core[1]; curr.u32 = * log++; core[1] = curr.u32; for (i = 0; i < 4; i++) { if (curr.u8[i] < prev.u8[i]) delta.u8[i] = curr.u8[i] + (max8 - prev.u8[i]); else delta.u8[i] = (curr.u8[i] - prev.u8[i]); bytes += sprintf(p + bytes, "%4u ", delta.u8[i]); } cm3_cnts.u32 = delta.u32; } { /* Extract the foldcnt from arg0 */ uint8 curr, prev, delta, max8 = ~0; bcm_buzzz_arg0_t arg0; arg0.u32 = *log; prev = core[2]; curr = arg0.klog.cnt; core[2] = curr; if (curr < prev) delta = curr + (max8 - prev); else delta = (curr - prev); bytes += sprintf(p + bytes, "%4u ", delta); foldcnt = delta; } instrcnt = cyccnt - (cm3_cnts.u8[0] + cm3_cnts.u8[1] + cm3_cnts.u8[2] + cm3_cnts.u8[3]) + foldcnt; if (instrcnt > 0xFFFFFF00) bytes += sprintf(p + bytes, "[%10s] ", "~"); else bytes += sprintf(p + bytes, "[%10u] ", instrcnt); return bytes; } int dhd_buzzz_dump_log(char *p, uint32 *core, uint32 *log, bcm_buzzz_t *buzzz) { int bytes = 0; bcm_buzzz_arg0_t arg0; static uint8 * fmt[] = BCM_BUZZZ_FMT_STRINGS; if (buzzz->counters == 6) { bytes += dhd_bcm_buzzz_dump_cntrs6(p, core, log); log += 2; /* 32bit cyccnt + (4 x 8bit) CM3 */ } else { bytes += dhd_buzzz_dump_cntrs(p, core, log, buzzz->counters); log += buzzz->counters; /* (N x 32bit) CR4=3, CA7=4 */ } /* Dump the logged arguments using the registered formats */ arg0.u32 = *log++; switch (arg0.klog.args) { case 0: bytes += sprintf(p + bytes, fmt[arg0.klog.id]); break; case 1: { uint32 arg1 = *log++; bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1); break; } case 2: { uint32 arg1, arg2; arg1 = *log++; arg2 = *log++; bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2); break; } case 3: { uint32 arg1, arg2, arg3; arg1 = *log++; arg2 = *log++; arg3 = *log++; bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3); break; } case 4: { uint32 arg1, arg2, arg3, arg4; arg1 = *log++; arg2 = *log++; arg3 = *log++; arg4 = *log++; bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3, arg4); break; } default: printf("Maximum one argument supported\n"); break; } bytes += sprintf(p + bytes, "\n"); return bytes; } void dhd_buzzz_dump(bcm_buzzz_t *buzzz_p, void *buffer_p, char *p) { int i; uint32 total, part1, part2, log_sz, core[BCM_BUZZZ_COUNTERS_MAX]; void * log; for (i = 0; i < BCM_BUZZZ_COUNTERS_MAX; i++) { core[i] = 0; } log_sz = buzzz_p->log_sz; part1 = ((uint32)buzzz_p->cur - (uint32)buzzz_p->log) / log_sz; if (buzzz_p->wrap == TRUE) { part2 = ((uint32)buzzz_p->end - (uint32)buzzz_p->cur) / log_sz; total = (buzzz_p->buffer_sz - BCM_BUZZZ_LOGENTRY_MAXSZ) / log_sz; } else { part2 = 0U; total = buzzz_p->count; } if (total == 0U) { printf("bcm_buzzz_dump total<%u> done\n", total); return; } else { printf("bcm_buzzz_dump total<%u> : part2<%u> + part1<%u>\n", total, part2, part1); } if (part2) { /* with wrap */ log = (void*)((size_t)buffer_p + (buzzz_p->cur - buzzz_p->log)); while (part2--) { /* from cur to end : part2 */ p[0] = '\0'; dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p); printf("%s", p); log = (void*)((size_t)log + buzzz_p->log_sz); } } log = (void*)buffer_p; while (part1--) { p[0] = '\0'; dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p); printf("%s", p); log = (void*)((size_t)log + buzzz_p->log_sz); } printf("bcm_buzzz_dump done.\n"); } int dhd_buzzz_dump_dngl(dhd_bus_t *bus) { bcm_buzzz_t * buzzz_p = NULL; void * buffer_p = NULL; char * page_p = NULL; pciedev_shared_t *sh; int ret = 0; if (bus->dhd->busstate != DHD_BUS_DATA) { return BCME_UNSUPPORTED; } if ((page_p = (char *)MALLOC(bus->dhd->osh, 4096)) == NULL) { printf("Page memory allocation failure\n"); goto done; } if ((buzzz_p = MALLOC(bus->dhd->osh, sizeof(bcm_buzzz_t))) == NULL) { printf("BCM BUZZZ memory allocation failure\n"); goto done; } ret = dhdpcie_readshared(bus); if (ret < 0) { DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__)); goto done; } sh = bus->pcie_sh; DHD_INFO(("%s buzzz:%08x\n", __FUNCTION__, sh->buzzz)); if (sh->buzzz != 0U) { /* Fetch and display dongle BUZZZ Trace */ dhdpcie_bus_membytes(bus, FALSE, (ulong)sh->buzzz, (uint8 *)buzzz_p, sizeof(bcm_buzzz_t)); printf("BUZZZ[0x%08x]: log<0x%08x> cur<0x%08x> end<0x%08x> " "count<%u> status<%u> wrap<%u>\n" "cpu<0x%02X> counters<%u> group<%u> buffer_sz<%u> log_sz<%u>\n", (int)sh->buzzz, (int)buzzz_p->log, (int)buzzz_p->cur, (int)buzzz_p->end, buzzz_p->count, buzzz_p->status, buzzz_p->wrap, buzzz_p->cpu_idcode, buzzz_p->counters, buzzz_p->group, buzzz_p->buffer_sz, buzzz_p->log_sz); if (buzzz_p->count == 0) { printf("Empty dongle BUZZZ trace\n\n"); goto done; } /* Allocate memory for trace buffer and format strings */ buffer_p = MALLOC(bus->dhd->osh, buzzz_p->buffer_sz); if (buffer_p == NULL) { printf("Buffer memory allocation failure\n"); goto done; } /* Fetch the trace. format strings are exported via bcm_buzzz.h */ dhdpcie_bus_membytes(bus, FALSE, (uint32)buzzz_p->log, /* Trace */ (uint8 *)buffer_p, buzzz_p->buffer_sz); /* Process and display the trace using formatted output */ { int ctr; for (ctr = 0; ctr < buzzz_p->counters; ctr++) { printf(" ", buzzz_p->eventid[ctr]); } printf("\n"); } dhd_buzzz_dump(buzzz_p, buffer_p, page_p); printf("----- End of dongle BCM BUZZZ Trace -----\n\n"); MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); buffer_p = NULL; } done: if (page_p) MFREE(bus->dhd->osh, page_p, 4096); if (buzzz_p) MFREE(bus->dhd->osh, buzzz_p, sizeof(bcm_buzzz_t)); if (buffer_p) MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); return BCME_OK; } #endif /* BCM_BUZZZ */ #define PCIE_GEN2(sih) ((BUSTYPE((sih)->bustype) == PCI_BUS) && \ ((sih)->buscoretype == PCIE2_CORE_ID)) static bool pcie2_mdiosetblock(dhd_bus_t *bus, uint blk) { uint mdiodata, mdioctrl, i = 0; uint pcie_serdes_spinwait = 200; mdioctrl = MDIOCTL2_DIVISOR_VAL | (0x1F << MDIOCTL2_REGADDR_SHF); mdiodata = (blk << MDIODATA2_DEVADDR_SHF) | MDIODATA2_DONE; si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdioctrl); si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0, mdiodata); OSL_DELAY(10); /* retry till the transaction is complete */ while (i < pcie_serdes_spinwait) { uint mdioctrl_read = si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, 0, 0); if (!(mdioctrl_read & MDIODATA2_DONE)) { break; } OSL_DELAY(1000); i++; } if (i >= pcie_serdes_spinwait) { DHD_ERROR(("pcie_mdiosetblock: timed out\n")); return FALSE; } return TRUE; } int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag) { dhd_bus_t *bus = dhdp->bus; int bcmerror = 0; unsigned long flags; #ifdef CONFIG_ARCH_MSM int retry = POWERUP_MAX_RETRY; #endif /* CONFIG_ARCH_MSM */ if (dhd_download_fw_on_driverload) { bcmerror = dhd_bus_start(dhdp); } else { if (flag == TRUE) { /* Turn off WLAN */ /* Removing Power */ DHD_INFO(("%s: == Power OFF ==\n", __FUNCTION__)); bus->dhd->up = FALSE; if (bus->dhd->busstate != DHD_BUS_DOWN) { dhdpcie_advertise_bus_cleanup(bus->dhd); if (bus->intr) { dhdpcie_free_irq(bus); } #ifdef BCMPCIE_OOB_HOST_WAKE /* Clean up any pending host wake IRQ */ dhd_bus_oob_intr_set(bus->dhd, FALSE); dhd_bus_oob_intr_unregister(bus->dhd); #endif /* BCMPCIE_OOB_HOST_WAKE */ dhd_os_wd_timer(dhdp, 0); dhd_bus_stop(bus, TRUE); dhd_prot_reset(dhdp); dhd_clear(dhdp); dhd_bus_release_dongle(bus); dhdpcie_bus_free_resource(bus); bcmerror = dhdpcie_bus_disable_device(bus); if (bcmerror) { DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", __FUNCTION__, bcmerror)); goto done; } #ifdef CONFIG_ARCH_MSM bcmerror = dhdpcie_bus_clock_stop(bus); if (bcmerror) { DHD_ERROR(("%s: host clock stop failed: %d\n", __FUNCTION__, bcmerror)); goto done; } #endif /* CONFIG_ARCH_MSM */ DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DOWN; DHD_GENERAL_UNLOCK(bus->dhd, flags); } else { if (bus->intr) { dhdpcie_free_irq(bus); } #ifdef BCMPCIE_OOB_HOST_WAKE /* Clean up any pending host wake IRQ */ dhd_bus_oob_intr_set(bus->dhd, FALSE); dhd_bus_oob_intr_unregister(bus->dhd); #endif /* BCMPCIE_OOB_HOST_WAKE */ dhd_prot_reset(dhdp); dhd_clear(dhdp); dhd_bus_release_dongle(bus); dhdpcie_bus_free_resource(bus); bcmerror = dhdpcie_bus_disable_device(bus); if (bcmerror) { DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", __FUNCTION__, bcmerror)); goto done; } #ifdef CONFIG_ARCH_MSM bcmerror = dhdpcie_bus_clock_stop(bus); if (bcmerror) { DHD_ERROR(("%s: host clock stop failed: %d\n", __FUNCTION__, bcmerror)); goto done; } #endif /* CONFIG_ARCH_MSM */ } bus->dhd->dongle_reset = TRUE; DHD_INFO(("%s: WLAN OFF Done\n", __FUNCTION__)); } else { /* Turn on WLAN */ if (bus->dhd->busstate == DHD_BUS_DOWN) { /* Powering On */ DHD_INFO(("%s: == Power ON ==\n", __FUNCTION__)); #ifdef CONFIG_ARCH_MSM while (--retry) { bcmerror = dhdpcie_bus_clock_start(bus); if (!bcmerror) { DHD_ERROR(("%s: dhdpcie_bus_clock_start OK\n", __FUNCTION__)); break; } else { OSL_SLEEP(10); } } if (bcmerror && !retry) { DHD_ERROR(("%s: host pcie clock enable failed: %d\n", __FUNCTION__, bcmerror)); goto done; } #endif /* CONFIG_ARCH_MSM */ bus->is_linkdown = 0; bus->pci_d3hot_done = 0; bcmerror = dhdpcie_bus_enable_device(bus); if (bcmerror) { DHD_ERROR(("%s: host configuration restore failed: %d\n", __FUNCTION__, bcmerror)); goto done; } bcmerror = dhdpcie_bus_alloc_resource(bus); if (bcmerror) { DHD_ERROR(("%s: dhdpcie_bus_resource_alloc failed: %d\n", __FUNCTION__, bcmerror)); goto done; } bcmerror = dhdpcie_bus_dongle_attach(bus); if (bcmerror) { DHD_ERROR(("%s: dhdpcie_bus_dongle_attach failed: %d\n", __FUNCTION__, bcmerror)); goto done; } bcmerror = dhd_bus_request_irq(bus); if (bcmerror) { DHD_ERROR(("%s: dhd_bus_request_irq failed: %d\n", __FUNCTION__, bcmerror)); goto done; } bus->dhd->dongle_reset = FALSE; bcmerror = dhd_bus_start(dhdp); if (bcmerror) { DHD_ERROR(("%s: dhd_bus_start: %d\n", __FUNCTION__, bcmerror)); goto done; } bus->dhd->up = TRUE; DHD_INFO(("%s: WLAN Power On Done\n", __FUNCTION__)); } else { DHD_ERROR(("%s: what should we do here\n", __FUNCTION__)); goto done; } } } done: if (bcmerror) { DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DOWN; DHD_GENERAL_UNLOCK(bus->dhd, flags); } return bcmerror; } static int pcie2_mdioop(dhd_bus_t *bus, uint physmedia, uint regaddr, bool write, uint *val, bool slave_bypass) { uint pcie_serdes_spinwait = 200, i = 0, mdio_ctrl; uint32 reg32; pcie2_mdiosetblock(bus, physmedia); /* enable mdio access to SERDES */ mdio_ctrl = MDIOCTL2_DIVISOR_VAL; mdio_ctrl |= (regaddr << MDIOCTL2_REGADDR_SHF); if (slave_bypass) mdio_ctrl |= MDIOCTL2_SLAVE_BYPASS; if (!write) mdio_ctrl |= MDIOCTL2_READ; si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdio_ctrl); if (write) { reg32 = PCIE2_MDIO_WR_DATA; si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0, *val | MDIODATA2_DONE); } else reg32 = PCIE2_MDIO_RD_DATA; /* retry till the transaction is complete */ while (i < pcie_serdes_spinwait) { uint done_val = si_corereg(bus->sih, bus->sih->buscoreidx, reg32, 0, 0); if (!(done_val & MDIODATA2_DONE)) { if (!write) { *val = si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_RD_DATA, 0, 0); *val = *val & MDIODATA2_MASK; } return 0; } OSL_DELAY(1000); i++; } return -1; } static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name, void *params, int plen, void *arg, int len, int val_size) { int bcmerror = 0; int32 int_val = 0; int32 int_val2 = 0; int32 int_val3 = 0; bool bool_val = 0; DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n", __FUNCTION__, actionid, name, params, plen, arg, len, val_size)); if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0) goto exit; if (plen >= (int)sizeof(int_val)) bcopy(params, &int_val, sizeof(int_val)); if (plen >= (int)sizeof(int_val) * 2) bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2)); if (plen >= (int)sizeof(int_val) * 3) bcopy((void*)((uintptr)params + 2 * sizeof(int_val)), &int_val3, sizeof(int_val3)); bool_val = (int_val != 0) ? TRUE : FALSE; /* Check if dongle is in reset. If so, only allow DEVRESET iovars */ if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) || actionid == IOV_GVAL(IOV_DEVRESET))) { bcmerror = BCME_NOTREADY; goto exit; } switch (actionid) { case IOV_SVAL(IOV_VARS): bcmerror = dhdpcie_downloadvars(bus, arg, len); break; case IOV_SVAL(IOV_PCIEREG): si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, int_val); si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0, int_val2); break; case IOV_GVAL(IOV_PCIEREG): si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, int_val); int_val = si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0); bcopy(&int_val, arg, sizeof(int_val)); break; case IOV_SVAL(IOV_PCIECOREREG): si_corereg(bus->sih, bus->sih->buscoreidx, int_val, ~0, int_val2); break; case IOV_GVAL(IOV_BAR0_SECWIN_REG): { sdreg_t sdreg; uint32 addr, size; bcopy(params, &sdreg, sizeof(sdreg)); addr = sdreg.offset; size = sdreg.func; if (si_backplane_access(bus->sih, addr, size, &int_val, TRUE) != BCME_OK) { DHD_ERROR(("Invalid size/addr combination \n")); bcmerror = BCME_ERROR; break; } bcopy(&int_val, arg, sizeof(int32)); break; } case IOV_SVAL(IOV_BAR0_SECWIN_REG): { sdreg_t sdreg; uint32 addr, size; bcopy(params, &sdreg, sizeof(sdreg)); addr = sdreg.offset; size = sdreg.func; if (si_backplane_access(bus->sih, addr, size, &sdreg.value, FALSE) != BCME_OK) { DHD_ERROR(("Invalid size/addr combination \n")); bcmerror = BCME_ERROR; } break; } case IOV_GVAL(IOV_SBREG): { sdreg_t sdreg; uint32 addr, size; bcopy(params, &sdreg, sizeof(sdreg)); addr = sdreg.offset | SI_ENUM_BASE; size = sdreg.func; if (si_backplane_access(bus->sih, addr, size, &int_val, TRUE) != BCME_OK) { DHD_ERROR(("Invalid size/addr combination \n")); bcmerror = BCME_ERROR; break; } bcopy(&int_val, arg, sizeof(int32)); break; } case IOV_SVAL(IOV_SBREG): { sdreg_t sdreg; uint32 addr, size; bcopy(params, &sdreg, sizeof(sdreg)); addr = sdreg.offset | SI_ENUM_BASE; size = sdreg.func; if (si_backplane_access(bus->sih, addr, size, &sdreg.value, FALSE) != BCME_OK) { DHD_ERROR(("Invalid size/addr combination \n")); bcmerror = BCME_ERROR; } break; } case IOV_GVAL(IOV_PCIESERDESREG): { uint val; if (!PCIE_GEN2(bus->sih)) { DHD_ERROR(("supported only in pcie gen2\n")); bcmerror = BCME_ERROR; break; } if (!pcie2_mdioop(bus, int_val, int_val2, FALSE, &val, FALSE)) { bcopy(&val, arg, sizeof(int32)); } else { DHD_ERROR(("pcie2_mdioop failed.\n")); bcmerror = BCME_ERROR; } break; } case IOV_SVAL(IOV_PCIESERDESREG): if (!PCIE_GEN2(bus->sih)) { DHD_ERROR(("supported only in pcie gen2\n")); bcmerror = BCME_ERROR; break; } if (pcie2_mdioop(bus, int_val, int_val2, TRUE, &int_val3, FALSE)) { DHD_ERROR(("pcie2_mdioop failed.\n")); bcmerror = BCME_ERROR; } break; case IOV_GVAL(IOV_PCIECOREREG): int_val = si_corereg(bus->sih, bus->sih->buscoreidx, int_val, 0, 0); bcopy(&int_val, arg, sizeof(int_val)); break; case IOV_SVAL(IOV_PCIECFGREG): OSL_PCI_WRITE_CONFIG(bus->osh, int_val, 4, int_val2); break; case IOV_GVAL(IOV_PCIECFGREG): int_val = OSL_PCI_READ_CONFIG(bus->osh, int_val, 4); bcopy(&int_val, arg, sizeof(int_val)); break; case IOV_SVAL(IOV_PCIE_LPBK): bcmerror = dhdpcie_bus_lpback_req(bus, int_val); break; case IOV_SVAL(IOV_PCIE_DMAXFER): bcmerror = dhdpcie_bus_dmaxfer_req(bus, int_val, int_val2, int_val3); break; case IOV_GVAL(IOV_PCIE_SUSPEND): int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_PCIE_SUSPEND): dhdpcie_bus_suspend(bus, bool_val); break; case IOV_GVAL(IOV_MEMSIZE): int_val = (int32)bus->ramsize; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_MEMBYTES): case IOV_GVAL(IOV_MEMBYTES): { uint32 address; /* absolute backplane address */ uint size, dsize; uint8 *data; bool set = (actionid == IOV_SVAL(IOV_MEMBYTES)); ASSERT(plen >= 2*sizeof(int)); address = (uint32)int_val; bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val)); size = (uint)int_val; /* Do some validation */ dsize = set ? plen - (2 * sizeof(int)) : len; if (dsize < size) { DHD_ERROR(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n", __FUNCTION__, (set ? "set" : "get"), address, size, dsize)); bcmerror = BCME_BADARG; break; } DHD_INFO(("%s: Request to %s %d bytes at address 0x%08x\n dsize %d ", __FUNCTION__, (set ? "write" : "read"), size, address, dsize)); /* check if CR4 */ if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) || si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) { /* if address is 0, store the reset instruction to be written in 0 */ if (set && address == bus->dongle_ram_base) { bus->resetinstr = *(((uint32*)params) + 2); } } else { /* If we know about SOCRAM, check for a fit */ if ((bus->orig_ramsize) && ((address > bus->orig_ramsize) || (address + size > bus->orig_ramsize))) { uint8 enable, protect, remap; si_socdevram(bus->sih, FALSE, &enable, &protect, &remap); if (!enable || protect) { DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d bytes at 0x%08x\n", __FUNCTION__, bus->orig_ramsize, size, address)); DHD_ERROR(("%s: socram enable %d, protect %d\n", __FUNCTION__, enable, protect)); bcmerror = BCME_BADARG; break; } if (!REMAP_ENAB(bus) && (address >= SOCDEVRAM_ARM_ADDR)) { uint32 devramsize = si_socdevram_size(bus->sih); if ((address < SOCDEVRAM_ARM_ADDR) || (address + size > (SOCDEVRAM_ARM_ADDR + devramsize))) { DHD_ERROR(("%s: bad address 0x%08x, size 0x%08x\n", __FUNCTION__, address, size)); DHD_ERROR(("%s: socram range 0x%08x,size 0x%08x\n", __FUNCTION__, SOCDEVRAM_ARM_ADDR, devramsize)); bcmerror = BCME_BADARG; break; } /* move it such that address is real now */ address -= SOCDEVRAM_ARM_ADDR; address += SOCDEVRAM_BP_ADDR; DHD_INFO(("%s: Request to %s %d bytes @ Mapped address 0x%08x\n", __FUNCTION__, (set ? "write" : "read"), size, address)); } else if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address) && remap) { /* Can not access remap region while devram remap bit is set * ROM content would be returned in this case */ DHD_ERROR(("%s: Need to disable remap for address 0x%08x\n", __FUNCTION__, address)); bcmerror = BCME_ERROR; break; } } } /* Generate the actual data pointer */ data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg; /* Call to do the transfer */ bcmerror = dhdpcie_bus_membytes(bus, set, address, data, size); break; } #ifdef BCM_BUZZZ /* Dump dongle side buzzz trace to console */ case IOV_GVAL(IOV_BUZZZ_DUMP): bcmerror = dhd_buzzz_dump_dngl(bus); break; #endif /* BCM_BUZZZ */ case IOV_SVAL(IOV_SET_DOWNLOAD_STATE): bcmerror = dhdpcie_bus_download_state(bus, bool_val); break; case IOV_GVAL(IOV_RAMSIZE): int_val = (int32)bus->ramsize; bcopy(&int_val, arg, val_size); break; case IOV_GVAL(IOV_RAMSTART): int_val = (int32)bus->dongle_ram_base; bcopy(&int_val, arg, val_size); break; case IOV_GVAL(IOV_CC_NVMSHADOW): { struct bcmstrbuf dump_b; bcm_binit(&dump_b, arg, len); bcmerror = dhdpcie_cc_nvmshadow(bus, &dump_b); break; } case IOV_GVAL(IOV_SLEEP_ALLOWED): bool_val = bus->sleep_allowed; bcopy(&bool_val, arg, val_size); break; case IOV_SVAL(IOV_SLEEP_ALLOWED): bus->sleep_allowed = bool_val; break; case IOV_GVAL(IOV_DONGLEISOLATION): int_val = bus->dhd->dongle_isolation; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_DONGLEISOLATION): bus->dhd->dongle_isolation = bool_val; break; case IOV_GVAL(IOV_LTRSLEEPON_UNLOOAD): int_val = bus->ltrsleep_on_unload; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_LTRSLEEPON_UNLOOAD): bus->ltrsleep_on_unload = bool_val; break; case IOV_GVAL(IOV_DUMP_RINGUPD_BLOCK): { struct bcmstrbuf dump_b; bcm_binit(&dump_b, arg, len); bcmerror = dhd_prot_ringupd_dump(bus->dhd, &dump_b); break; } case IOV_GVAL(IOV_DMA_RINGINDICES): { int h2d_support, d2h_support; d2h_support = DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) ? 1 : 0; h2d_support = DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support) ? 1 : 0; int_val = d2h_support | (h2d_support << 1); bcopy(&int_val, arg, sizeof(int_val)); break; } case IOV_SVAL(IOV_DMA_RINGINDICES): /* Can change it only during initialization/FW download */ if (bus->dhd->busstate == DHD_BUS_DOWN) { if ((int_val > 3) || (int_val < 0)) { DHD_ERROR(("Bad argument. Possible values: 0, 1, 2 & 3\n")); bcmerror = BCME_BADARG; } else { bus->dhd->dma_d2h_ring_upd_support = (int_val & 1) ? TRUE : FALSE; bus->dhd->dma_h2d_ring_upd_support = (int_val & 2) ? TRUE : FALSE; } } else { DHD_ERROR(("%s: Can change only when bus down (before FW download)\n", __FUNCTION__)); bcmerror = BCME_NOTDOWN; } break; case IOV_GVAL(IOV_METADATA_DBG): int_val = dhd_prot_metadata_dbg_get(bus->dhd); bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_METADATA_DBG): dhd_prot_metadata_dbg_set(bus->dhd, (int_val != 0)); break; case IOV_GVAL(IOV_RX_METADATALEN): int_val = dhd_prot_metadatalen_get(bus->dhd, TRUE); bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_RX_METADATALEN): if (int_val > 64) { bcmerror = BCME_BUFTOOLONG; break; } dhd_prot_metadatalen_set(bus->dhd, int_val, TRUE); break; case IOV_SVAL(IOV_TXP_THRESHOLD): dhd_prot_txp_threshold(bus->dhd, TRUE, int_val); break; case IOV_GVAL(IOV_TXP_THRESHOLD): int_val = dhd_prot_txp_threshold(bus->dhd, FALSE, int_val); bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_DB1_FOR_MB): if (int_val) bus->db1_for_mb = TRUE; else bus->db1_for_mb = FALSE; break; case IOV_GVAL(IOV_DB1_FOR_MB): if (bus->db1_for_mb) int_val = 1; else int_val = 0; bcopy(&int_val, arg, val_size); break; case IOV_GVAL(IOV_TX_METADATALEN): int_val = dhd_prot_metadatalen_get(bus->dhd, FALSE); bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_TX_METADATALEN): if (int_val > 64) { bcmerror = BCME_BUFTOOLONG; break; } dhd_prot_metadatalen_set(bus->dhd, int_val, FALSE); break; case IOV_SVAL(IOV_DEVRESET): dhd_bus_devreset(bus->dhd, (uint8)bool_val); break; case IOV_GVAL(IOV_FLOW_PRIO_MAP): int_val = bus->dhd->flow_prio_map_type; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_FLOW_PRIO_MAP): int_val = (int32)dhd_update_flow_prio_map(bus->dhd, (uint8)int_val); bcopy(&int_val, arg, val_size); break; #ifdef DHD_PCIE_RUNTIMEPM case IOV_GVAL(IOV_IDLETIME): int_val = bus->idletime; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_IDLETIME): if (int_val < 0) { bcmerror = BCME_BADARG; } else { bus->idletime = int_val; } break; #endif /* DHD_PCIE_RUNTIMEPM */ case IOV_GVAL(IOV_TXBOUND): int_val = (int32)dhd_txbound; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_TXBOUND): dhd_txbound = (uint)int_val; break; case IOV_GVAL(IOV_RXBOUND): int_val = (int32)dhd_rxbound; bcopy(&int_val, arg, val_size); break; case IOV_SVAL(IOV_RXBOUND): dhd_rxbound = (uint)int_val; break; case IOV_SVAL(IOV_HANGREPORT): bus->dhd->hang_report = bool_val; DHD_ERROR(("%s: Set hang_report as %d\n", __FUNCTION__, bus->dhd->hang_report)); break; case IOV_GVAL(IOV_HANGREPORT): int_val = (int32)bus->dhd->hang_report; bcopy(&int_val, arg, val_size); break; default: bcmerror = BCME_UNSUPPORTED; break; } exit: return bcmerror; } /* dhdpcie_bus_doiovar */ /** Transfers bytes from host to dongle using pio mode */ static int dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 len) { if (bus->dhd == NULL) { DHD_ERROR(("bus not inited\n")); return 0; } if (bus->dhd->prot == NULL) { DHD_ERROR(("prot is not inited\n")); return 0; } if (bus->dhd->busstate != DHD_BUS_DATA) { DHD_ERROR(("not in a readystate to LPBK is not inited\n")); return 0; } dhdmsgbuf_lpbk_req(bus->dhd, len); return 0; } int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state) { int timeleft; unsigned long flags; int rc = 0; if (bus->dhd == NULL) { DHD_ERROR(("bus not inited\n")); return BCME_ERROR; } if (bus->dhd->prot == NULL) { DHD_ERROR(("prot is not inited\n")); return BCME_ERROR; } if (dhd_query_bus_erros(bus->dhd)) { return BCME_ERROR; } DHD_GENERAL_LOCK(bus->dhd, flags); if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) { DHD_ERROR(("not in a readystate to LPBK is not inited\n")); DHD_GENERAL_UNLOCK(bus->dhd, flags); return BCME_ERROR; } DHD_GENERAL_UNLOCK(bus->dhd, flags); if (bus->dhd->dongle_reset) { DHD_ERROR(("Dongle is in reset state.\n")); return -EIO; } if (bus->suspended == state) { /* Set to same state */ DHD_ERROR(("Bus is already in SUSPEND state.\n")); return BCME_OK; } if (state) { int idle_retry = 0; int active; if (bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down, state=%d\n", __FUNCTION__, state)); return BCME_ERROR; } /* Suspend */ DHD_ERROR(("%s: Entering suspend state\n", __FUNCTION__)); bus->wait_for_d3_ack = 0; bus->suspended = TRUE; DHD_GENERAL_LOCK(bus->dhd, flags); /* stop all interface network queue. */ dhd_bus_stop_queue(bus); bus->dhd->busstate = DHD_BUS_SUSPEND; if (bus->dhd->dhd_bus_busy_state & DHD_BUS_BUSY_IN_TX) { DHD_ERROR(("Tx Request is not ended\n")); bus->dhd->busstate = DHD_BUS_DATA; /* resume all interface network queue. */ dhd_bus_start_queue(bus); DHD_GENERAL_UNLOCK(bus->dhd, flags); bus->suspended = FALSE; return -EBUSY; } bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SUSPEND; DHD_GENERAL_UNLOCK(bus->dhd, flags); DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); dhd_os_set_ioctl_resp_timeout(D3_ACK_RESP_TIMEOUT); dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM); timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack); dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT); DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); { uint32 d2h_mb_data = 0; uint32 zero = 0; /* If wait_for_d3_ack was not updated because D2H MB was not received */ if (bus->wait_for_d3_ack == 0) { /* Read the Mb data to see if the Dongle has actually sent D3 ACK */ dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0); if (!D2H_DEV_MB_INVALIDATED(d2h_mb_data) && (d2h_mb_data & D2H_DEV_D3_ACK)) { DHD_ERROR(("*** D3 WAR for missing interrupt ***\r\n")); /* Clear the MB Data */ dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0); /* Consider that D3 ACK is received */ bus->wait_for_d3_ack = 1; bus->d3_ack_war_cnt++; } /* d2h_mb_data & D2H_DEV_D3_ACK */ } /* bus->wait_for_d3_ack was 0 */ } /* To allow threads that got pre-empted to complete. */ while ((active = dhd_os_check_wakelock_all(bus->dhd)) && (idle_retry < MAX_WKLK_IDLE_CHECK)) { msleep(1); idle_retry++; } if (bus->wait_for_d3_ack) { DHD_ERROR(("%s: Got D3 Ack \n", __FUNCTION__)); /* Got D3 Ack. Suspend the bus */ if (active) { DHD_ERROR(("%s():Suspend failed because of wakelock restoring " "Dongle to D0\n", __FUNCTION__)); /* * Dongle still thinks that it has to be in D3 state * until gets a D0 Inform, but we are backing off from suspend. * Ensure that Dongle is brought back to D0. * * Bringing back Dongle from D3 Ack state to D0 state * is a 2 step process. Dongle would want to know that D0 Inform * would be sent as a MB interrupt * to bring it out of D3 Ack state to D0 state. * So we have to send both this message. */ DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM_IN_USE | H2D_HOST_D0_INFORM)); DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); bus->suspended = FALSE; DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DATA; /* resume all interface network queue. */ dhd_bus_start_queue(bus); DHD_GENERAL_UNLOCK(bus->dhd, flags); rc = BCME_ERROR; } else { DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM_IN_USE)); DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); dhdpcie_bus_intr_disable(bus); rc = dhdpcie_pci_suspend_resume(bus, state); dhd_bus_set_device_wake(bus, FALSE); } bus->dhd->d3ackcnt_timeout = 0; #if defined(BCMPCIE_OOB_HOST_WAKE) dhdpcie_oob_intr_set(bus, TRUE); #endif /* BCMPCIE_OOB_HOST_WAKE */ } else if (timeleft == 0) { bus->dhd->d3ack_timeout_occured = TRUE; bus->dhd->d3ackcnt_timeout++; DHD_ERROR(("%s: resumed on timeout for D3 ACK d3_inform_cnt %d \n", __FUNCTION__, bus->dhd->d3ackcnt_timeout)); dhd_prot_debug_info_print(bus->dhd); #ifdef DHD_FW_COREDUMP if (bus->dhd->memdump_enabled) { /* write core dump to file */ bus->dhd->memdump_type = DUMP_TYPE_D3_ACK_TIMEOUT; dhdpcie_mem_dump(bus); } #endif /* DHD_FW_COREDUMP */ bus->suspended = FALSE; DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DATA; /* resume all interface network queue. */ dhd_bus_start_queue(bus); DHD_GENERAL_UNLOCK(bus->dhd, flags); if (bus->dhd->d3ackcnt_timeout >= MAX_CNTL_D3ACK_TIMEOUT) { DHD_ERROR(("%s: Event HANG send up " "due to PCIe linkdown\n", __FUNCTION__)); #ifdef SUPPORT_LINKDOWN_RECOVERY #ifdef CONFIG_ARCH_MSM bus->no_cfg_restore = 1; #endif /* CONFIG_ARCH_MSM */ #endif /* SUPPORT_LINKDOWN_RECOVERY */ dhd_os_check_hang(bus->dhd, 0, -ETIMEDOUT); } rc = -ETIMEDOUT; } bus->wait_for_d3_ack = 1; DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SUSPEND; dhd_os_busbusy_wake(bus->dhd); DHD_GENERAL_UNLOCK(bus->dhd, flags); } else { /* Resume */ #if defined(BCMPCIE_OOB_HOST_WAKE) DHD_OS_OOB_IRQ_WAKE_UNLOCK(bus->dhd); #endif /* BCMPCIE_OOB_HOST_WAKE */ DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_RESUME; DHD_GENERAL_UNLOCK(bus->dhd, flags); rc = dhdpcie_pci_suspend_resume(bus, state); if (bus->dhd->busstate == DHD_BUS_SUSPEND) { DHD_OS_WAKE_LOCK_WAIVE(bus->dhd); dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM)); DHD_OS_WAKE_LOCK_RESTORE(bus->dhd); dhd_bus_set_device_wake(bus, TRUE); } bus->suspended = FALSE; DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->busstate = DHD_BUS_DATA; bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_RESUME; #ifdef DHD_PCIE_RUNTIMEPM if (bus->dhd->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_SUSPEND_DONE) { bus->bus_wake = 1; OSL_SMP_WMB(); wake_up_interruptible(&bus->rpm_queue); } #endif /* DHD_PCIE_RUNTIMEPM */ /* resume all interface network queue. */ dhd_bus_start_queue(bus); dhd_os_busbusy_wake(bus->dhd); DHD_GENERAL_UNLOCK(bus->dhd, flags); dhdpcie_bus_intr_enable(bus); } return rc; } /** Transfers bytes from host to dongle and to host again using DMA */ static int dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus, uint32 len, uint32 srcdelay, uint32 destdelay) { if (bus->dhd == NULL) { DHD_ERROR(("bus not inited\n")); return BCME_ERROR; } if (bus->dhd->prot == NULL) { DHD_ERROR(("prot is not inited\n")); return BCME_ERROR; } if (bus->dhd->busstate != DHD_BUS_DATA) { DHD_ERROR(("not in a readystate to LPBK is not inited\n")); return BCME_ERROR; } if (len < 5 || len > 4194296) { DHD_ERROR(("len is too small or too large\n")); return BCME_ERROR; } return dhdmsgbuf_dmaxfer_req(bus->dhd, len, srcdelay, destdelay); } static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter) { int bcmerror = 0; uint32 *cr4_regs; if (!bus->sih) { DHD_ERROR(("%s: NULL sih!!\n", __FUNCTION__)); return BCME_ERROR; } /* To enter download state, disable ARM and reset SOCRAM. * To exit download state, simply reset ARM (default is RAM boot). */ if (enter) { bus->alp_only = TRUE; /* some chips (e.g. 43602) have two ARM cores, the CR4 is receives the firmware. */ cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) && !(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { /* Halt ARM & remove reset */ si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT); if (!(si_setcore(bus->sih, SYSMEM_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find SYSMEM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } si_core_reset(bus->sih, 0, 0); /* reset last 4 bytes of RAM address. to be used for shared area */ dhdpcie_init_shared_addr(bus); } else if (cr4_regs == NULL) { /* no CR4 present on chip */ si_core_disable(bus->sih, 0); if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } si_core_reset(bus->sih, 0, 0); /* Clear the top bit of memory */ if (bus->ramsize) { uint32 zeros = 0; if (dhdpcie_bus_membytes(bus, TRUE, bus->ramsize - 4, (uint8*)&zeros, 4) < 0) { bcmerror = BCME_ERROR; goto fail; } } } else { /* For CR4, * Halt ARM * Remove ARM reset * Read RAM base address [0x18_0000] * [next] Download firmware * [done at else] Populate the reset vector * [done at else] Remove ARM halt */ /* Halt ARM & remove reset */ si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT); if (BCM43602_CHIP(bus->sih->chip)) { W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 5); W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0); W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 7); W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0); } /* reset last 4 bytes of RAM address. to be used for shared area */ dhdpcie_init_shared_addr(bus); } } else { if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) { /* write vars */ if ((bcmerror = dhdpcie_bus_write_vars(bus))) { DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); goto fail; } /* switch back to arm core again */ if (!(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find ARM CA7 core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } /* write address 0 with reset instruction */ bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0, (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr)); /* now remove reset and halt and continue to run CA7 */ } else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } if (!si_iscoreup(bus->sih)) { DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } /* Enable remap before ARM reset but after vars. * No backplane access in remap mode */ if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) && !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) { DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } } else { if (BCM43602_CHIP(bus->sih->chip)) { /* Firmware crashes on SOCSRAM access when core is in reset */ if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } si_core_reset(bus->sih, 0, 0); si_setcore(bus->sih, ARMCR4_CORE_ID, 0); } /* write vars */ if ((bcmerror = dhdpcie_bus_write_vars(bus))) { DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); goto fail; } /* switch back to arm core again */ if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) { DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__)); bcmerror = BCME_ERROR; goto fail; } /* write address 0 with reset instruction */ bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0, (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr)); if (bcmerror == BCME_OK) { uint32 tmp; bcmerror = dhdpcie_bus_membytes(bus, FALSE, 0, (uint8 *)&tmp, sizeof(tmp)); if (bcmerror == BCME_OK && tmp != bus->resetinstr) { DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n", __FUNCTION__, bus->resetinstr)); DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n", __FUNCTION__, tmp)); bcmerror = BCME_ERROR; goto fail; } } /* now remove reset and halt and continue to run CR4 */ } si_core_reset(bus->sih, 0, 0); /* Allow HT Clock now that the ARM is running. */ bus->alp_only = FALSE; bus->dhd->busstate = DHD_BUS_LOAD; } fail: /* Always return to PCIE core */ si_setcore(bus->sih, PCIE2_CORE_ID, 0); return bcmerror; } /* dhdpcie_bus_download_state */ static int dhdpcie_bus_write_vars(dhd_bus_t *bus) { int bcmerror = 0; uint32 varsize, phys_size; uint32 varaddr; uint8 *vbuffer; uint32 varsizew; #ifdef DHD_DEBUG uint8 *nvram_ularray; #endif /* DHD_DEBUG */ /* Even if there are no vars are to be written, we still need to set the ramsize. */ varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0; varaddr = (bus->ramsize - 4) - varsize; varaddr += bus->dongle_ram_base; if (bus->vars) { vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize); if (!vbuffer) return BCME_NOMEM; bzero(vbuffer, varsize); bcopy(bus->vars, vbuffer, bus->varsz); /* Write the vars list */ DHD_INFO_HW4(("%s: tcm: %p varaddr: 0x%x varsize: %d\n", __FUNCTION__, bus->tcm, varaddr, varsize)); bcmerror = dhdpcie_bus_membytes(bus, TRUE, varaddr, vbuffer, varsize); /* Implement read back and verify later */ #ifdef DHD_DEBUG /* Verify NVRAM bytes */ DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize)); nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize); if (!nvram_ularray) { MFREE(bus->dhd->osh, vbuffer, varsize); return BCME_NOMEM; } /* Upload image to verify downloaded contents. */ memset(nvram_ularray, 0xaa, varsize); /* Read the vars list to temp buffer for comparison */ bcmerror = dhdpcie_bus_membytes(bus, FALSE, varaddr, nvram_ularray, varsize); if (bcmerror) { DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n", __FUNCTION__, bcmerror, varsize, varaddr)); } /* Compare the org NVRAM with the one read from RAM */ if (memcmp(vbuffer, nvram_ularray, varsize)) { DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__)); } else DHD_INFO(("%s: Download, Upload and compare of NVRAM succeeded.\n", __FUNCTION__)); MFREE(bus->dhd->osh, nvram_ularray, varsize); #endif /* DHD_DEBUG */ MFREE(bus->dhd->osh, vbuffer, varsize); } phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize; phys_size += bus->dongle_ram_base; /* adjust to the user specified RAM */ DHD_INFO(("Physical memory size: %d, usable memory size: %d\n", phys_size, bus->ramsize)); DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize)); varsize = ((phys_size - 4) - varaddr); /* * Determine the length token: * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits. */ if (bcmerror) { varsizew = 0; bus->nvram_csm = varsizew; } else { varsizew = varsize / 4; varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF); bus->nvram_csm = varsizew; varsizew = htol32(varsizew); } DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew)); /* Write the length token to the last word */ DHD_INFO_HW4(("%s: tcm: %p phys_size: 0x%x varsizew: %x\n", __FUNCTION__, bus->tcm, phys_size, varsizew)); bcmerror = dhdpcie_bus_membytes(bus, TRUE, (phys_size - 4), (uint8*)&varsizew, 4); return bcmerror; } /* dhdpcie_bus_write_vars */ int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len) { int bcmerror = BCME_OK; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); /* Basic sanity checks */ if (bus->dhd->up) { bcmerror = BCME_NOTDOWN; goto err; } if (!len) { bcmerror = BCME_BUFTOOSHORT; goto err; } /* Free the old ones and replace with passed variables */ if (bus->vars) MFREE(bus->dhd->osh, bus->vars, bus->varsz); bus->vars = MALLOC(bus->dhd->osh, len); bus->varsz = bus->vars ? len : 0; if (bus->vars == NULL) { bcmerror = BCME_NOMEM; goto err; } /* Copy the passed variables, which should include the terminating double-null */ bcopy(arg, bus->vars, bus->varsz); err: return bcmerror; } #ifndef BCMPCIE_OOB_HOST_WAKE /* loop through the capability list and see if the pcie capabilty exists */ uint8 dhdpcie_find_pci_capability(osl_t *osh, uint8 req_cap_id) { uint8 cap_id; uint8 cap_ptr = 0; uint8 byte_val; /* check for Header type 0 */ byte_val = read_pci_cfg_byte(PCI_CFG_HDR); if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) { DHD_ERROR(("%s : PCI config header not normal.\n", __FUNCTION__)); goto end; } /* check if the capability pointer field exists */ byte_val = read_pci_cfg_byte(PCI_CFG_STAT); if (!(byte_val & PCI_CAPPTR_PRESENT)) { DHD_ERROR(("%s : PCI CAP pointer not present.\n", __FUNCTION__)); goto end; } cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR); /* check if the capability pointer is 0x00 */ if (cap_ptr == 0x00) { DHD_ERROR(("%s : PCI CAP pointer is 0x00.\n", __FUNCTION__)); goto end; } /* loop thr'u the capability list and see if the pcie capabilty exists */ cap_id = read_pci_cfg_byte(cap_ptr); while (cap_id != req_cap_id) { cap_ptr = read_pci_cfg_byte((cap_ptr + 1)); if (cap_ptr == 0x00) break; cap_id = read_pci_cfg_byte(cap_ptr); } end: return cap_ptr; } void dhdpcie_pme_active(osl_t *osh, bool enable) { uint8 cap_ptr; uint32 pme_csr; cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID); if (!cap_ptr) { DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__)); return; } pme_csr = OSL_PCI_READ_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32)); DHD_ERROR(("%s : pme_sts_ctrl 0x%x\n", __FUNCTION__, pme_csr)); pme_csr |= PME_CSR_PME_STAT; if (enable) { pme_csr |= PME_CSR_PME_EN; } else { pme_csr &= ~PME_CSR_PME_EN; } OSL_PCI_WRITE_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32), pme_csr); } bool dhdpcie_pme_cap(osl_t *osh) { uint8 cap_ptr; uint32 pme_cap; cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID); if (!cap_ptr) { DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__)); return FALSE; } pme_cap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32)); DHD_ERROR(("%s : pme_cap 0x%x\n", __FUNCTION__, pme_cap)); return ((pme_cap & PME_CAP_PM_STATES) != 0); } #endif /* !BCMPCIE_OOB_HOST_WAKE */ void dhd_dump_intr_registers(dhd_pub_t *dhd, struct bcmstrbuf *strbuf) { uint32 intstatus = 0; uint32 intmask = 0; uint32 mbintstatus = 0; uint32 d2h_mb_data = 0; intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0); intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0); mbintstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCID2H_MailBox, 0, 0); dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0); bcm_bprintf(strbuf, "intstatus=0x%x intmask=0x%x mbintstatus=0x%x\n", intstatus, intmask, mbintstatus); bcm_bprintf(strbuf, "d2h_mb_data=0x%x def_intmask=0x%x\n", d2h_mb_data, dhd->bus->def_intmask); } /** Add bus dump output to a buffer */ void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf) { uint16 flowid; int ix = 0; flow_ring_node_t *flow_ring_node; flow_info_t *flow_info; char eabuf[ETHER_ADDR_STR_LEN]; if (dhdp->busstate != DHD_BUS_DATA) return; dhd_prot_print_info(dhdp, strbuf); dhd_dump_intr_registers(dhdp, strbuf); bcm_bprintf(strbuf, "h2d_mb_data_ptr_addr 0x%x, d2h_mb_data_ptr_addr 0x%x\n", dhdp->bus->h2d_mb_data_ptr_addr, dhdp->bus->d2h_mb_data_ptr_addr); bcm_bprintf(strbuf, "dhd cumm_ctr %d\n", DHD_CUMM_CTR_READ(&dhdp->cumm_ctr)); bcm_bprintf(strbuf, "%s %4s %2s %4s %17s %4s %4s %10s %4s %4s %17s %17s %7s ", "Num:", "Flow", "If", "Prio", ":Dest_MacAddress:", "Qlen", "CLen", "Overflows", "RD", "WR", "BASE(VA)", "BASE(PA)", "SIZE"); bcm_bprintf(strbuf, "%5s %6s %5s \n", "Acked", "tossed", "noack"); for (flowid = 0; flowid < dhdp->num_flow_rings; flowid++) { flow_ring_node = DHD_FLOW_RING(dhdp, flowid); if (flow_ring_node->active) { flow_info = &flow_ring_node->flow_info; bcm_bprintf(strbuf, "%3d. %4d %2d %4d %17s %4d %4d %10u ", ix++, flow_ring_node->flowid, flow_info->ifindex, flow_info->tid, bcm_ether_ntoa((struct ether_addr *)&flow_info->da, eabuf), DHD_FLOW_QUEUE_LEN(&flow_ring_node->queue), DHD_CUMM_CTR_READ(DHD_FLOW_QUEUE_CLEN_PTR(&flow_ring_node->queue)), DHD_FLOW_QUEUE_FAILURES(&flow_ring_node->queue)); dhd_prot_print_flow_ring(dhdp, flow_ring_node->prot_info, strbuf, "%4d %4d %17p %8x:%8x %7d "); bcm_bprintf(strbuf, "%5s %6s %5s\n", "NA", "NA", "NA"); } } bcm_bprintf(strbuf, "D3 inform cnt %d\n", dhdp->bus->d3_inform_cnt); bcm_bprintf(strbuf, "D0 inform cnt %d\n", dhdp->bus->d0_inform_cnt); bcm_bprintf(strbuf, "D0 inform in use cnt %d\n", dhdp->bus->d0_inform_in_use_cnt); bcm_bprintf(strbuf, "D3 Ack WAR cnt %d\n", dhdp->bus->d3_ack_war_cnt); } /** * Brings transmit packets on all flow rings closer to the dongle, by moving (a subset) from their * flow queue to their flow ring. */ static void dhd_update_txflowrings(dhd_pub_t *dhd) { unsigned long flags; dll_t *item, *next; flow_ring_node_t *flow_ring_node; struct dhd_bus *bus = dhd->bus; DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); for (item = dll_head_p(&bus->const_flowring); (!dhd_is_device_removed(dhd) && !dll_end(&bus->const_flowring, item)); item = next) { if (dhd->hang_was_sent) { break; } next = dll_next_p(item); flow_ring_node = dhd_constlist_to_flowring(item); /* Ensure that flow_ring_node in the list is Not Null */ ASSERT(flow_ring_node != NULL); /* Ensure that the flowring node has valid contents */ ASSERT(flow_ring_node->prot_info != NULL); dhd_prot_update_txflowring(dhd, flow_ring_node->flowid, flow_ring_node->prot_info); } DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); } /** Mailbox ringbell Function */ static void dhd_bus_gen_devmb_intr(struct dhd_bus *bus) { if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { DHD_ERROR(("mailbox communication not supported\n")); return; } if (bus->db1_for_mb) { /* this is a pcie core register, not the config register */ DHD_INFO(("writing a mail box interrupt to the device, through doorbell 1\n")); si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_DB1, ~0, 0x12345678); } else { DHD_INFO(("writing a mail box interrupt to the device, through config space\n")); dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0)); dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0)); } } static void dhd_bus_set_device_wake(struct dhd_bus *bus, bool val) { if (bus->device_wake_state != val) { DHD_INFO(("Set Device_Wake to %d\n", val)); #ifdef PCIE_OOB if (bus->oob_enabled) { if (val) { gpio_port = gpio_port | (1 << DEVICE_WAKE); gpio_write_port_non_block(gpio_handle_val, gpio_port); } else { gpio_port = gpio_port & (0xff ^ (1 << DEVICE_WAKE)); gpio_write_port_non_block(gpio_handle_val, gpio_port); } } #endif /* PCIE_OOB */ bus->device_wake_state = val; } } #ifdef PCIE_OOB void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val) { DHD_INFO(("Set Device_Wake to %d\n", val)); if (val) { gpio_port = gpio_port | (1 << BIT_BT_REG_ON); gpio_write_port(gpio_handle_val, gpio_port); } else { gpio_port = gpio_port & (0xff ^ (1 << BIT_BT_REG_ON)); gpio_write_port(gpio_handle_val, gpio_port); } } int dhd_oob_get_bt_reg_on(struct dhd_bus *bus) { int ret; uint8 val; ret = gpio_read_port(gpio_handle_val, &val); if (ret < 0) { DHD_ERROR(("gpio_read_port returns %d\n", ret)); return ret; } if (val & (1 << BIT_BT_REG_ON)) { ret = 1; } else { ret = 0; } return ret; } static void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus) { if (dhd_doorbell_timeout) dhd_timeout_start(&bus->doorbell_timer, (dhd_doorbell_timeout * 1000) / dhd_watchdog_ms); else if (!(bus->dhd->busstate == DHD_BUS_SUSPEND)) dhd_bus_set_device_wake(bus, FALSE); } #endif /* PCIE_OOB */ /** mailbox doorbell ring function */ void dhd_bus_ringbell(struct dhd_bus *bus, uint32 value) { if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, PCIE_INTB, PCIE_INTB); } else { /* this is a pcie core register, not the config regsiter */ DHD_INFO(("writing a door bell to the device\n")); si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_MailBox, ~0, 0x12345678); } } void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value) { #ifdef PCIE_OOB dhd_bus_set_device_wake(bus, TRUE); dhd_bus_doorbell_timeout_reset(bus); #endif W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, value); } static void dhd_bus_ringbell_oldpcie(struct dhd_bus *bus, uint32 value) { uint32 w; w = (R_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr) & ~PCIE_INTB) | PCIE_INTB; W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, w); } dhd_mb_ring_t dhd_bus_get_mbintr_fn(struct dhd_bus *bus) { if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt); if (bus->pcie_mb_intr_addr) { bus->pcie_mb_intr_osh = si_osh(bus->sih); return dhd_bus_ringbell_oldpcie; } } else { bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx, PCIH2D_MailBox); if (bus->pcie_mb_intr_addr) { bus->pcie_mb_intr_osh = si_osh(bus->sih); return dhdpcie_bus_ringbell_fast; } } return dhd_bus_ringbell; } bool BCMFASTPATH dhd_bus_dpc(struct dhd_bus *bus) { bool resched = FALSE; /* Flag indicating resched wanted */ unsigned long flags; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); DHD_GENERAL_LOCK(bus->dhd, flags); /* Check for only DHD_BUS_DOWN and not for DHD_BUS_DOWN_IN_PROGRESS * to avoid IOCTL Resumed On timeout when ioctl is waiting for response * and rmmod is fired in parallel, which will make DHD_BUS_DOWN_IN_PROGRESS * and if we return from here, then IOCTL response will never be handled */ if (bus->dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__)); bus->intstatus = 0; DHD_GENERAL_UNLOCK(bus->dhd, flags); return 0; } bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DPC; DHD_GENERAL_UNLOCK(bus->dhd, flags); resched = dhdpcie_bus_process_mailbox_intr(bus, bus->intstatus); if (!resched) { bus->intstatus = 0; if (!bus->pci_d3hot_done) { dhdpcie_bus_intr_enable(bus); } else { DHD_ERROR(("%s: dhdpcie_bus_intr_enable skip in pci D3hot state \n", __FUNCTION__)); } } DHD_GENERAL_LOCK(bus->dhd, flags); bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DPC; dhd_os_busbusy_wake(bus->dhd); DHD_GENERAL_UNLOCK(bus->dhd, flags); return resched; } static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data) { uint32 cur_h2d_mb_data = 0; DHD_INFO_HW4(("%s: H2D_MB_DATA: 0x%08X\n", __FUNCTION__, h2d_mb_data)); if (bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); return; } dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0); if (cur_h2d_mb_data != 0) { uint32 i = 0; DHD_INFO(("GRRRRRRR: MB transaction is already pending 0x%04x\n", cur_h2d_mb_data)); while ((i++ < 100) && cur_h2d_mb_data) { OSL_DELAY(10); dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0); } if (i >= 100) { DHD_ERROR(("%s : waited 1ms for the dngl " "to ack the previous mb transaction\n", __FUNCTION__)); DHD_ERROR(("%s : MB transaction is still pending 0x%04x\n", __FUNCTION__, cur_h2d_mb_data)); } } dhd_bus_cmn_writeshared(bus, &h2d_mb_data, sizeof(uint32), H2D_MB_DATA, 0); dhd_bus_gen_devmb_intr(bus); if (h2d_mb_data == H2D_HOST_D3_INFORM) { DHD_INFO_HW4(("%s: send H2D_HOST_D3_INFORM to dongle\n", __FUNCTION__)); bus->d3_inform_cnt++; } if (h2d_mb_data == H2D_HOST_D0_INFORM_IN_USE) { DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM_IN_USE to dongle\n", __FUNCTION__)); bus->d0_inform_in_use_cnt++; } if (h2d_mb_data == H2D_HOST_D0_INFORM) { DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM to dongle\n", __FUNCTION__)); bus->d0_inform_cnt++; } } static void dhdpcie_handle_mb_data(dhd_bus_t *bus) { uint32 d2h_mb_data = 0; uint32 zero = 0; dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0); if (D2H_DEV_MB_INVALIDATED(d2h_mb_data)) { DHD_INFO_HW4(("%s: Invalid D2H_MB_DATA: 0x%08x\n", __FUNCTION__, d2h_mb_data)); return; } dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0); DHD_INFO_HW4(("D2H_MB_DATA: 0x%08x\n", d2h_mb_data)); if (d2h_mb_data & D2H_DEV_FWHALT) { DHD_ERROR(("FW trap has happened\n")); dhdpcie_checkdied(bus, NULL, 0); /* not ready yet dhd_os_ind_firmware_stall(bus->dhd); */ return; } if (d2h_mb_data & D2H_DEV_DS_ENTER_REQ) { /* what should we do */ DHD_INFO(("D2H_MB_DATA: DEEP SLEEP REQ\n")); dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK); DHD_INFO(("D2H_MB_DATA: sent DEEP SLEEP ACK\n")); } if (d2h_mb_data & D2H_DEV_DS_EXIT_NOTE) { /* what should we do */ DHD_INFO(("D2H_MB_DATA: DEEP SLEEP EXIT\n")); } if (d2h_mb_data & D2H_DEV_D3_ACK) { /* what should we do */ DHD_INFO_HW4(("D2H_MB_DATA: D3 ACK\n")); if (!bus->wait_for_d3_ack) { bus->wait_for_d3_ack = 1; dhd_os_d3ack_wake(bus->dhd); } } } /* Inform Dongle to print HW Registers for Livelock Debug */ void dhdpcie_bus_dongle_print_hwregs(struct dhd_bus *bus) { dhdpcie_send_mb_data(bus, H2D_FW_TRAP); } static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus) { bool resched = FALSE; if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4)) { /* Msg stream interrupt */ if (intstatus & I_BIT1) { resched = dhdpci_bus_read_frames(bus); } else if (intstatus & I_BIT0) { /* do nothing for Now */ } } else { if (intstatus & (PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1)) dhdpcie_handle_mb_data(bus); if (bus->dhd->busstate == DHD_BUS_SUSPEND) { goto exit; } if (intstatus & PCIE_MB_D2H_MB_MASK) { resched = dhdpci_bus_read_frames(bus); } } exit: return resched; } static bool dhdpci_bus_read_frames(dhd_bus_t *bus) { bool more = FALSE; /* There may be frames in both ctrl buf and data buf; check ctrl buf first */ DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); dhd_prot_process_ctrlbuf(bus->dhd); /* Unlock to give chance for resp to be handled */ DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); /* update the flow ring cpls */ dhd_update_txflowrings(bus->dhd); /* With heavy TX traffic, we could get a lot of TxStatus * so add bound */ more |= dhd_prot_process_msgbuf_txcpl(bus->dhd, dhd_txbound); /* With heavy RX traffic, this routine potentially could spend some time * processing RX frames without RX bound */ more |= dhd_prot_process_msgbuf_rxcpl(bus->dhd, dhd_rxbound); /* don't talk to the dongle if fw is about to be reloaded */ if (bus->dhd->hang_was_sent) { more = FALSE; } DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT)); return more; } bool dhdpcie_tcm_valid(dhd_bus_t *bus) { uint32 addr = 0; int rv; uint32 shaddr = 0; pciedev_shared_t sh; shaddr = bus->dongle_ram_base + bus->ramsize - 4; /* Read last word in memory to determine address of pciedev_shared structure */ addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr)); if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) || (addr > shaddr)) { DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid addr\n", __FUNCTION__, addr)); return FALSE; } /* Read hndrte_shared structure */ if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&sh, sizeof(pciedev_shared_t))) < 0) { DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv)); return FALSE; } /* Compare any field in pciedev_shared_t */ if (sh.console_addr != bus->pcie_sh->console_addr) { DHD_ERROR(("Contents of pciedev_shared_t structure are not matching.\n")); return FALSE; } return TRUE; } static bool dhdpcie_check_firmware_compatible(uint32 firmware_api_version, uint32 host_api_version) { DHD_INFO(("firmware api revision %d, host api revision %d\n", firmware_api_version, host_api_version)); if (firmware_api_version <= host_api_version) return TRUE; if ((firmware_api_version == 6) && (host_api_version == 5)) return TRUE; if ((firmware_api_version == 5) && (host_api_version == 6)) return TRUE; return FALSE; } static int dhdpcie_readshared(dhd_bus_t *bus) { uint32 addr = 0; int rv, dma_indx_wr_buf, dma_indx_rd_buf; uint32 shaddr = 0; pciedev_shared_t *sh = bus->pcie_sh; dhd_timeout_t tmo; shaddr = bus->dongle_ram_base + bus->ramsize - 4; DHD_INFO_HW4(("%s: ram_base: 0x%x ramsize 0x%x tcm: %p shaddr: 0x%x nvram_csm: 0x%x\n", __FUNCTION__, bus->dongle_ram_base, bus->ramsize, bus->tcm, shaddr, bus->nvram_csm)); /* start a timer for 5 seconds */ dhd_timeout_start(&tmo, MAX_READ_TIMEOUT); while (((addr == 0) || (addr == bus->nvram_csm)) && !dhd_timeout_expired(&tmo)) { /* Read last word in memory to determine address of pciedev_shared structure */ addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr)); } if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) || (addr > shaddr)) { DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid\n", __FUNCTION__, addr)); DHD_ERROR(("Waited %u usec, dongle is not ready\n", tmo.elapsed)); return BCME_ERROR; } else { bus->shared_addr = (ulong)addr; DHD_INFO(("PCIe shared addr (0x%08x) read took %u usec " "before dongle is ready\n", addr, tmo.elapsed)); } /* Read hndrte_shared structure */ if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(pciedev_shared_t))) < 0) { DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv)); return rv; } /* Endianness */ sh->flags = ltoh32(sh->flags); sh->trap_addr = ltoh32(sh->trap_addr); sh->assert_exp_addr = ltoh32(sh->assert_exp_addr); sh->assert_file_addr = ltoh32(sh->assert_file_addr); sh->assert_line = ltoh32(sh->assert_line); sh->console_addr = ltoh32(sh->console_addr); sh->msgtrace_addr = ltoh32(sh->msgtrace_addr); sh->dma_rxoffset = ltoh32(sh->dma_rxoffset); sh->rings_info_ptr = ltoh32(sh->rings_info_ptr); #ifdef DHD_DEBUG /* load bus console address */ bus->console_addr = sh->console_addr; #endif /* Read the dma rx offset */ bus->dma_rxoffset = bus->pcie_sh->dma_rxoffset; dhd_prot_rx_dataoffset(bus->dhd, bus->dma_rxoffset); DHD_INFO(("DMA RX offset from shared Area %d\n", bus->dma_rxoffset)); if (!(dhdpcie_check_firmware_compatible(sh->flags & PCIE_SHARED_VERSION_MASK, PCIE_SHARED_VERSION))) { DHD_ERROR(("%s: pcie_shared version %d in dhd " "is older than pciedev_shared version %d in dongle\n", __FUNCTION__, PCIE_SHARED_VERSION, sh->flags & PCIE_SHARED_VERSION_MASK)); return BCME_ERROR; } bus->rw_index_sz = (sh->flags & PCIE_SHARED_2BYTE_INDICES) ? sizeof(uint16) : sizeof(uint32); DHD_INFO(("%s: Dongle advertizes %d size indices\n", __FUNCTION__, bus->rw_index_sz)); /* Does the FW support DMA'ing r/w indices */ if (sh->flags & PCIE_SHARED_DMA_INDEX) { DHD_ERROR(("%s: Host support DMAing indices: H2D:%d - D2H:%d. FW supports it\n", __FUNCTION__, (DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support) ? 1 : 0), (DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) ? 1 : 0))); } else if (DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) || DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support)) { #ifdef BCM_INDX_DMA DHD_ERROR(("%s: Incompatible FW. FW does not support DMAing indices\n", __FUNCTION__)); return BCME_ERROR; #endif DHD_ERROR(("%s: Host supports DMAing indices but FW does not\n", __FUNCTION__)); bus->dhd->dma_d2h_ring_upd_support = FALSE; bus->dhd->dma_h2d_ring_upd_support = FALSE; } /* get ring_info, ring_state and mb data ptrs and store the addresses in bus structure */ { ring_info_t ring_info; if ((rv = dhdpcie_bus_membytes(bus, FALSE, sh->rings_info_ptr, (uint8 *)&ring_info, sizeof(ring_info_t))) < 0) return rv; bus->h2d_mb_data_ptr_addr = ltoh32(sh->h2d_mb_data_ptr); bus->d2h_mb_data_ptr_addr = ltoh32(sh->d2h_mb_data_ptr); bus->max_sub_queues = ltoh16(ring_info.max_sub_queues); /* If both FW and Host support DMA'ing indices, allocate memory and notify FW * The max_sub_queues is read from FW initialized ring_info */ if (DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support)) { dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, H2D_DMA_INDX_WR_BUF, bus->max_sub_queues); dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, D2H_DMA_INDX_RD_BUF, BCMPCIE_D2H_COMMON_MSGRINGS); if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) { DHD_ERROR(("%s: Failed to allocate memory for dma'ing h2d indices" "Host will use w/r indices in TCM\n", __FUNCTION__)); bus->dhd->dma_h2d_ring_upd_support = FALSE; } } if (DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support)) { dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, D2H_DMA_INDX_WR_BUF, BCMPCIE_D2H_COMMON_MSGRINGS); dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz, H2D_DMA_INDX_RD_BUF, bus->max_sub_queues); if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) { DHD_ERROR(("%s: Failed to allocate memory for dma'ing d2h indices" "Host will use w/r indices in TCM\n", __FUNCTION__)); bus->dhd->dma_d2h_ring_upd_support = FALSE; } } /* read ringmem and ringstate ptrs from shared area and store in host variables */ dhd_fillup_ring_sharedptr_info(bus, &ring_info); bcm_print_bytes("ring_info_raw", (uchar *)&ring_info, sizeof(ring_info_t)); DHD_INFO(("ring_info\n")); DHD_INFO(("%s: max H2D queues %d\n", __FUNCTION__, ltoh16(ring_info.max_sub_queues))); DHD_INFO(("mail box address\n")); DHD_INFO(("%s: h2d_mb_data_ptr_addr 0x%04x\n", __FUNCTION__, bus->h2d_mb_data_ptr_addr)); DHD_INFO(("%s: d2h_mb_data_ptr_addr 0x%04x\n", __FUNCTION__, bus->d2h_mb_data_ptr_addr)); } bus->dhd->d2h_sync_mode = sh->flags & PCIE_SHARED_D2H_SYNC_MODE_MASK; DHD_INFO(("%s: d2h_sync_mode 0x%08x\n", __FUNCTION__, bus->dhd->d2h_sync_mode)); return BCME_OK; } /* dhdpcie_readshared */ /** Read ring mem and ring state ptr info from shared memory area in device memory */ static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info) { uint16 i = 0; uint16 j = 0; uint32 tcm_memloc; uint32 d2h_w_idx_ptr, d2h_r_idx_ptr, h2d_w_idx_ptr, h2d_r_idx_ptr; /* Ring mem ptr info */ /* Alloated in the order H2D_MSGRING_CONTROL_SUBMIT 0 H2D_MSGRING_RXPOST_SUBMIT 1 D2H_MSGRING_CONTROL_COMPLETE 2 D2H_MSGRING_TX_COMPLETE 3 D2H_MSGRING_RX_COMPLETE 4 */ { /* ringmemptr holds start of the mem block address space */ tcm_memloc = ltoh32(ring_info->ringmem_ptr); /* Find out ringmem ptr for each ring common ring */ for (i = 0; i <= BCMPCIE_COMMON_MSGRING_MAX_ID; i++) { bus->ring_sh[i].ring_mem_addr = tcm_memloc; /* Update mem block */ tcm_memloc = tcm_memloc + sizeof(ring_mem_t); DHD_INFO(("ring id %d ring mem addr 0x%04x \n", i, bus->ring_sh[i].ring_mem_addr)); } } /* Ring state mem ptr info */ { d2h_w_idx_ptr = ltoh32(ring_info->d2h_w_idx_ptr); d2h_r_idx_ptr = ltoh32(ring_info->d2h_r_idx_ptr); h2d_w_idx_ptr = ltoh32(ring_info->h2d_w_idx_ptr); h2d_r_idx_ptr = ltoh32(ring_info->h2d_r_idx_ptr); /* Store h2d common ring write/read pointers */ for (i = 0; i < BCMPCIE_H2D_COMMON_MSGRINGS; i++) { bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr; bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr; /* update mem block */ h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz; h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz; DHD_INFO(("h2d w/r : idx %d write %x read %x \n", i, bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); } /* Store d2h common ring write/read pointers */ for (j = 0; j < BCMPCIE_D2H_COMMON_MSGRINGS; j++, i++) { bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr; bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr; /* update mem block */ d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz; d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz; DHD_INFO(("d2h w/r : idx %d write %x read %x \n", i, bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); } /* Store txflow ring write/read pointers */ for (j = 0; j < (bus->max_sub_queues - BCMPCIE_H2D_COMMON_MSGRINGS); i++, j++) { bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr; bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr; /* update mem block */ h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz; h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz; DHD_INFO(("FLOW Rings h2d w/r : idx %d write %x read %x \n", i, bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r)); } } } /* dhd_fillup_ring_sharedptr_info */ /** * Initialize bus module: prepare for communication with the dongle. Called after downloading * firmware into the dongle. */ int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex) { dhd_bus_t *bus = dhdp->bus; int ret = 0; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); ASSERT(bus->dhd); if (!bus->dhd) return 0; /* Make sure we're talking to the core. */ bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0); ASSERT(bus->reg != NULL); /* before opening up bus for data transfer, check if shared are is intact */ ret = dhdpcie_readshared(bus); if (ret < 0) { DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__)); return ret; } /* Make sure we're talking to the core. */ bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0); ASSERT(bus->reg != NULL); /* Set bus state according to enable result */ dhdp->busstate = DHD_BUS_DATA; if (!dhd_download_fw_on_driverload) dhd_dpc_enable(bus->dhd); /* Enable the interrupt after device is up */ dhdpcie_bus_intr_enable(bus); /* bcmsdh_intr_unmask(bus->sdh); */ #ifdef DHD_PCIE_RUNTIMEPM bus->idlecount = 0; bus->idletime = (int32)MAX_IDLE_COUNT; init_waitqueue_head(&bus->rpm_queue); mutex_init(&bus->pm_lock); #endif /* DHD_PCIE_RUNTIMEPM */ bus->d3_ack_war_cnt = 0; return ret; } static void dhdpcie_init_shared_addr(dhd_bus_t *bus) { uint32 addr = 0; uint32 val = 0; addr = bus->dongle_ram_base + bus->ramsize - 4; #ifdef DHD_PCIE_RUNTIMEPM dhdpcie_runtime_bus_wake(bus->dhd, TRUE, __builtin_return_address(0)); #endif /* DHD_PCIE_RUNTIMEPM */ DHD_INFO_HW4(("%s: tcm: %p, addr: 0x%x val: 0x%x\n", __FUNCTION__, bus->tcm, addr, val)); dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val)); } bool dhdpcie_chipmatch(uint16 vendor, uint16 device) { if (vendor != PCI_VENDOR_ID_BROADCOM) { DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, vendor, device)); return (-ENODEV); } if ((device == BCM4350_D11AC_ID) || (device == BCM4350_D11AC2G_ID) || (device == BCM4350_D11AC5G_ID) || (device == BCM4350_CHIP_ID) || (device == BCM43569_CHIP_ID)) return 0; if ((device == BCM4354_D11AC_ID) || (device == BCM4354_D11AC2G_ID) || (device == BCM4354_D11AC5G_ID) || (device == BCM4354_CHIP_ID)) return 0; if ((device == BCM4356_D11AC_ID) || (device == BCM4356_D11AC2G_ID) || (device == BCM4356_D11AC5G_ID) || (device == BCM4356_CHIP_ID)) return 0; if ((device == BCM4345_D11AC_ID) || (device == BCM4345_D11AC2G_ID) || (device == BCM4345_D11AC5G_ID) || BCM4345_CHIP(device)) return 0; if ((device == BCM4335_D11AC_ID) || (device == BCM4335_D11AC2G_ID) || (device == BCM4335_D11AC5G_ID) || (device == BCM4335_CHIP_ID)) return 0; if ((device == BCM43602_D11AC_ID) || (device == BCM43602_D11AC2G_ID) || (device == BCM43602_D11AC5G_ID) || (device == BCM43602_CHIP_ID)) return 0; if ((device == BCM43569_D11AC_ID) || (device == BCM43569_D11AC2G_ID) || (device == BCM43569_D11AC5G_ID) || (device == BCM43569_CHIP_ID)) return 0; if ((device == BCM4358_D11AC_ID) || (device == BCM4358_D11AC2G_ID) || (device == BCM4358_D11AC5G_ID)) return 0; if ((device == BCM4349_D11AC_ID) || (device == BCM4349_D11AC2G_ID) || (device == BCM4349_D11AC5G_ID) || (device == BCM4349_CHIP_ID)) return 0; if ((device == BCM4355_D11AC_ID) || (device == BCM4355_D11AC2G_ID) || (device == BCM4355_D11AC5G_ID) || (device == BCM4355_CHIP_ID)) return 0; if ((device == BCM4359_D11AC_ID) || (device == BCM4359_D11AC2G_ID) || (device == BCM4359_D11AC5G_ID)) return 0; if ((device == BCM43596_D11AC_ID) || (device == BCM43596_D11AC2G_ID) || (device == BCM43596_D11AC5G_ID)) return 0; if ((device == BCM43597_D11AC_ID) || (device == BCM43597_D11AC2G_ID) || (device == BCM43597_D11AC5G_ID)) return 0; if ((device == BCM4365_D11AC_ID) || (device == BCM4365_D11AC2G_ID) || (device == BCM4365_D11AC5G_ID) || (device == BCM4365_CHIP_ID)) return 0; if ((device == BCM4366_D11AC_ID) || (device == BCM4366_D11AC2G_ID) || (device == BCM4366_D11AC5G_ID) || (device == BCM4366_CHIP_ID)) return 0; DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, vendor, device)); return (-ENODEV); } /* dhdpcie_chipmatch */ /** * Name: dhdpcie_cc_nvmshadow * * Description: * A shadow of OTP/SPROM exists in ChipCommon Region * betw. 0x800 and 0xBFF (Backplane Addr. 0x1800_0800 and 0x1800_0BFF). * Strapping option (SPROM vs. OTP), presence of OTP/SPROM and its size * can also be read from ChipCommon Registers. */ static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b) { uint16 dump_offset = 0; uint32 dump_size = 0, otp_size = 0, sprom_size = 0; /* Table for 65nm OTP Size (in bits) */ int otp_size_65nm[8] = {0, 2048, 4096, 8192, 4096, 6144, 512, 1024}; volatile uint16 *nvm_shadow; uint cur_coreid; uint chipc_corerev; chipcregs_t *chipcregs; /* Save the current core */ cur_coreid = si_coreid(bus->sih); /* Switch to ChipC */ chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0); ASSERT(chipcregs != NULL); chipc_corerev = si_corerev(bus->sih); /* Check ChipcommonCore Rev */ if (chipc_corerev < 44) { DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev)); return BCME_UNSUPPORTED; } /* Check ChipID */ if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip)) { DHD_ERROR(("%s: cc_nvmdump cmd. supported for 4350/4345 only\n", __FUNCTION__)); return BCME_UNSUPPORTED; } /* Check if SRC_PRESENT in SpromCtrl(0x190 in ChipCommon Regs) is set */ if (chipcregs->sromcontrol & SRC_PRESENT) { /* SPROM Size: 1Kbits (0x0), 4Kbits (0x1), 16Kbits(0x2) */ sprom_size = (1 << (2 * ((chipcregs->sromcontrol & SRC_SIZE_MASK) >> SRC_SIZE_SHIFT))) * 1024; bcm_bprintf(b, "\nSPROM Present (Size %d bits)\n", sprom_size); } if (chipcregs->sromcontrol & SRC_OTPPRESENT) { bcm_bprintf(b, "\nOTP Present"); if (((chipcregs->otplayout & OTPL_WRAP_TYPE_MASK) >> OTPL_WRAP_TYPE_SHIFT) == OTPL_WRAP_TYPE_40NM) { /* 40nm OTP: Size = (OtpSize + 1) * 1024 bits */ otp_size = (((chipcregs->capabilities & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) + 1) * 1024; bcm_bprintf(b, "(Size %d bits)\n", otp_size); } else { /* This part is untested since newer chips have 40nm OTP */ otp_size = otp_size_65nm[(chipcregs->capabilities & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT]; bcm_bprintf(b, "(Size %d bits)\n", otp_size); DHD_INFO(("%s: 65nm/130nm OTP Size not tested. \n", __FUNCTION__)); } } if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) && ((chipcregs->capabilities & CC_CAP_OTPSIZE) == 0)) { DHD_ERROR(("%s: SPROM and OTP could not be found \n", __FUNCTION__)); return BCME_NOTFOUND; } /* Check the strapping option in SpromCtrl: Set = OTP otherwise SPROM */ if ((chipcregs->sromcontrol & SRC_OTPSEL) && (chipcregs->sromcontrol & SRC_OTPPRESENT)) { bcm_bprintf(b, "OTP Strap selected.\n" "\nOTP Shadow in ChipCommon:\n"); dump_size = otp_size / 16 ; /* 16bit words */ } else if (((chipcregs->sromcontrol & SRC_OTPSEL) == 0) && (chipcregs->sromcontrol & SRC_PRESENT)) { bcm_bprintf(b, "SPROM Strap selected\n" "\nSPROM Shadow in ChipCommon:\n"); /* If SPROM > 8K only 8Kbits is mapped to ChipCommon (0x800 - 0xBFF) */ /* dump_size in 16bit words */ dump_size = sprom_size > 8 ? (8 * 1024) / 16 : sprom_size / 16; } else { DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n", __FUNCTION__)); return BCME_NOTFOUND; } if (bus->regs == NULL) { DHD_ERROR(("ChipCommon Regs. not initialized\n")); return BCME_NOTREADY; } else { bcm_bprintf(b, "\n OffSet:"); /* Point to the SPROM/OTP shadow in ChipCommon */ nvm_shadow = chipcregs->sromotp; /* * Read 16 bits / iteration. * dump_size & dump_offset in 16-bit words */ while (dump_offset < dump_size) { if (dump_offset % 2 == 0) /* Print the offset in the shadow space in Bytes */ bcm_bprintf(b, "\n 0x%04x", dump_offset * 2); bcm_bprintf(b, "\t0x%04x", *(nvm_shadow + dump_offset)); dump_offset += 0x1; } } /* Switch back to the original core */ si_setcore(bus->sih, cur_coreid, 0); return BCME_OK; } /* dhdpcie_cc_nvmshadow */ /** * Name: dhdpcie_sromotp_customvar * * Description: * read otp/sprom and parse & store customvar. * * A shadow of OTP/SPROM exists in ChipCommon Region * betw. 0x800 and 0xBFF (Backplane Addr. 0x1800_0800 and 0x1800_0BFF). * Strapping option (SPROM vs. OTP), presence of OTP/SPROM and its size * can also be read from ChipCommon Registers. */ static int dhdpcie_sromotp_customvar(dhd_bus_t *bus, uint32 *customvar1, uint32 *customvar2) { uint16 dump_offset = 0; uint32 dump_size = 0, otp_size = 0, sprom_size = 0; /* Table for 65nm OTP Size (in bits) */ int otp_size_65nm[8] = {0, 2048, 4096, 8192, 4096, 6144, 512, 1024}; #ifdef CUSTOMER_HW2 uint32 otp_start_addr; uint32 otp_end_addr; uint32 cur_addr; uint32 byte_enable; int delay; #else volatile uint16 *nvm_shadow; #endif /* CUSTOMER_HW2 */ uint cur_coreid; uint chipc_corerev; chipcregs_t *chipcregs; uint16 *otp_dump; uint8 *cis; uint8 tup, tlen; int i = 0; /* Save the current core */ cur_coreid = si_coreid(bus->sih); /* Switch to ChipC */ chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0); ASSERT(chipcregs != NULL); chipc_corerev = si_corerev(bus->sih); /* Check ChipcommonCore Rev */ if (chipc_corerev < 44) { DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev)); return BCME_UNSUPPORTED; } /* Check ChipID */ if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip) && ((uint16)bus->sih->chip != BCM4355_CHIP_ID) && ((uint16)bus->sih->chip != BCM4359_CHIP_ID) && ((uint16)bus->sih->chip != BCM4349_CHIP_ID)) { DHD_ERROR(("%s: supported for chips" "4350/4345/4355/4364/4349/4359 only\n", __FUNCTION__)); return BCME_UNSUPPORTED; } /* Check if SRC_PRESENT in SpromCtrl(0x190 in ChipCommon Regs) is set */ if (chipcregs->sromcontrol & SRC_PRESENT) { /* SPROM Size: 1Kbits (0x0), 4Kbits (0x1), 16Kbits(0x2) */ sprom_size = (1 << (2 * ((chipcregs->sromcontrol & SRC_SIZE_MASK) >> SRC_SIZE_SHIFT))) * 1024; DHD_TRACE(("\nSPROM Present (Size %d bits)\n", sprom_size)); } if (chipcregs->sromcontrol & SRC_OTPPRESENT) { DHD_TRACE(("\nOTP Present")); if (((chipcregs->otplayout & OTPL_WRAP_TYPE_MASK) >> OTPL_WRAP_TYPE_SHIFT) == OTPL_WRAP_TYPE_40NM) { /* 40nm OTP: Size = (OtpSize + 1) * 1024 bits */ /* Chipcommon rev51 is a variation on rev45 and does not support * the latest OTP configuration. */ if (chipc_corerev != 51 && chipc_corerev >= 49) { otp_size = (((chipcregs->otplayout & OTPL_ROW_SIZE_MASK) >> OTPL_ROW_SIZE_SHIFT) + 1) * 1024; DHD_TRACE(("(Size %d bits)\n", otp_size)); } else { otp_size = (((chipcregs->capabilities & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) + 1) * 1024; DHD_TRACE(("(Size %d bits)\n", otp_size)); } } else { /* This part is untested since newer chips have 40nm OTP */ /* Chipcommon rev51 is a variation on rev45 and does not support * the latest OTP configuration. */ if (chipc_corerev != 51 && chipc_corerev >= 49) { otp_size = otp_size_65nm[(chipcregs->otplayout & OTPL_ROW_SIZE_MASK) >> OTPL_ROW_SIZE_SHIFT]; DHD_TRACE(("(Size %d bits)\n", otp_size)); } else { otp_size = otp_size_65nm[(chipcregs->capabilities & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT]; DHD_TRACE(("(Size %d bits)\n", otp_size)); DHD_TRACE(("%s: 65nm/130nm OTP Size not tested. \n", __FUNCTION__)); } } } /* Chipcommon rev51 is a variation on rev45 and does not support * the latest OTP configuration. */ if (chipc_corerev != 51 && chipc_corerev >= 49) { if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) && ((chipcregs->otplayout & OTPL_ROW_SIZE_MASK) == 0)) { DHD_ERROR(("%s: SPROM and OTP could not be found " "sromcontrol = %x, otplayout = %x \n", __FUNCTION__, chipcregs->sromcontrol, chipcregs->otplayout)); return BCME_NOTFOUND; } } else { if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) && ((chipcregs->capabilities & CC_CAP_OTPSIZE) == 0)) { DHD_ERROR(("%s: SPROM and OTP could not be found " "sromcontrol = %x, capablities = %x \n", __FUNCTION__, chipcregs->sromcontrol, chipcregs->capabilities)); return BCME_NOTFOUND; } } /* Check the strapping option in SpromCtrl: Set = OTP otherwise SPROM */ if ((!(chipcregs->sromcontrol & SRC_PRESENT) || (chipcregs->sromcontrol & SRC_OTPSEL)) && (chipcregs->sromcontrol & SRC_OTPPRESENT)) { DHD_TRACE(("OTP Strap selected.\n" "\nOTP Shadow in ChipCommon:\n")); dump_size = otp_size / 16 ; /* 16bit words */ } else if (((chipcregs->sromcontrol & SRC_OTPSEL) == 0) && (chipcregs->sromcontrol & SRC_PRESENT)) { DHD_TRACE(("SPROM Strap selected\n" "\nSPROM Shadow in ChipCommon:\n")); /* If SPROM > 8K only 8Kbits is mapped to ChipCommon (0x800 - 0xBFF) */ /* dump_size in 16bit words */ dump_size = sprom_size > 8 ? (8 * 1024) / 16 : sprom_size / 16; } else { DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n", __FUNCTION__)); return BCME_NOTFOUND; } if (bus->regs == NULL) { DHD_ERROR(("ChipCommon Regs. not initialized\n")); return BCME_NOTREADY; } #ifdef CUSTOMER_HW2 /* Use CC backplane interconnect registers to read OTP region */ otp_start_addr = si_corebase(bus->sih, GCI_CORE_ID); if (!otp_start_addr) { DHD_ERROR(("%s: Failed to find gci core base addr\n", __FUNCTION__)); return BCME_NOTFOUND; } otp_dump = kzalloc(dump_size*2, GFP_KERNEL); if (otp_dump == NULL) { DHD_ERROR(("%s: Insufficient system memory of size %d\n", __FUNCTION__, dump_size)); return BCME_NOMEM; } /* Read 16 bits / iteration. * dump_size is in 16-bit words */ otp_end_addr = otp_start_addr + (dump_size * 2); cur_addr = otp_start_addr; /* ByteEnables(3:0) bits represent backplane address and data * locations to read/write in 4-byte width. */ byte_enable = 0x03; while (cur_addr < otp_end_addr) { W_REG(bus->osh, &chipcregs->bp_addrlow, cur_addr); W_REG(bus->osh, &chipcregs->bp_addrhigh, 0x0); /* 0x0200 will set StartBusy bit to start indirect backplane access */ W_REG(bus->osh, &chipcregs->bp_indaccess, 0x0200 | byte_enable); for (delay = 0; delay < STARTBUSY_BIT_POLL_MAX_TIME; delay++) { /* Hardware clears StartBusy bit on transfer completion */ if (R_REG(bus->osh, &chipcregs->bp_indaccess) == byte_enable) break; OSL_DELAY(100); } if (delay == STARTBUSY_BIT_POLL_MAX_TIME) { DHD_ERROR(("%s: Read from 0x%x didn't complete\n", __FUNCTION__, cur_addr)); if (otp_dump) { kfree(otp_dump); otp_dump = NULL; } return BCME_ERROR; } if (byte_enable == 0x03) { *(otp_dump + dump_offset) = R_REG(bus->osh, &chipcregs->bp_data) & 0xFFFF; byte_enable = 0x0c; } else { *(otp_dump + dump_offset) = (R_REG(bus->osh, &chipcregs->bp_data) >> 16) & 0xFFFF; byte_enable = 0x03; } cur_addr += 2; dump_offset += 1; } #else /* CUSTOMER_HW2 */ /* Chipcommon rev51 is a variation on rev45 and does not support * the latest OTP configuration. */ if (chipc_corerev != 51 && chipc_corerev >= 49) { /* Chip common can read only 8kbits, * for ccrev >= 49 otp size is around 12 kbits so use GCI core */ nvm_shadow = (volatile uint16 *)si_setcore(bus->sih, GCI_CORE_ID, 0); } else { /* Point to the SPROM/OTP shadow in ChipCommon */ nvm_shadow = chipcregs->sromotp; } if (nvm_shadow == NULL) { DHD_ERROR(("%s: NVM Shadow is not intialized\n", __FUNCTION__)); return BCME_NOTFOUND; } otp_dump = kzalloc(dump_size*2, GFP_KERNEL); if (otp_dump == NULL) { DHD_ERROR(("%s: Insufficient system memory of size %d\n", __FUNCTION__, dump_size)); return BCME_NOMEM; } /* * Read 16 bits / iteration. * dump_size & dump_offset in 16-bit words */ while (dump_offset < dump_size) { *(otp_dump + dump_offset) = *(nvm_shadow + dump_offset); dump_offset += 0x1; } #endif /* CUSTOMER_HW2 */ /* Read from cis tuple start address */ cis = (uint8 *)otp_dump + CISTPL_OFFSET; /* parse value of customvar2 tuple */ do { tup = cis[i++]; if (tup == CISTPL_NULL || tup == CISTPL_END) tlen = 0; else tlen = cis[i++]; if ((i + tlen) >= dump_size*2) break; switch (tup) { case CISTPL_BRCM_HNBU: switch (cis[i]) { case HNBU_CUSTOM1: *customvar1 = ((cis[i + 4] << 24) + (cis[i + 3] << 16) + (cis[i + 2] << 8) + cis[i + 1]); DHD_ERROR(("%s : customvar1 [%x]\n", __FUNCTION__, *customvar1)); break; case HNBU_CUSTOM2: *customvar2 = ((cis[i + 4] << 24) + (cis[i + 3] << 16) + (cis[i + 2] << 8) + cis[i + 1]); DHD_ERROR(("%s : customvar2 [%x]\n", __FUNCTION__, *customvar2)); break; default: break; } break; default: break; } i += tlen; } while (tup != 0xff); if (otp_dump) { kfree(otp_dump); otp_dump = NULL; } /* Switch back to the original core */ si_setcore(bus->sih, cur_coreid, 0); return BCME_OK; } /* dhdpcie_sromotp_customvar */ /** Flow rings are dynamically created and destroyed */ void dhd_bus_clean_flow_ring(dhd_bus_t *bus, void *node) { void *pkt; flow_queue_t *queue; flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)node; unsigned long flags; queue = &flow_ring_node->queue; #ifdef DHDTCPACK_SUPPRESS /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt, * when there is a newly coming packet from network stack. */ dhd_tcpack_info_tbl_clean(bus->dhd); #endif /* DHDTCPACK_SUPPRESS */ /* clean up BUS level info */ DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); /* Flush all pending packets in the queue, if any */ while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { PKTFREE(bus->dhd->osh, pkt, TRUE); } ASSERT(DHD_FLOW_QUEUE_EMPTY(queue)); flow_ring_node->status = FLOW_RING_STATUS_CLOSED; flow_ring_node->active = FALSE; DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); dll_delete(&flow_ring_node->list); DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); /* Release the flowring object back into the pool */ dhd_prot_flowrings_pool_release(bus->dhd, flow_ring_node->flowid, flow_ring_node->prot_info); /* Free the flowid back to the flowid allocator */ dhd_flowid_free(bus->dhd, flow_ring_node->flow_info.ifindex, flow_ring_node->flowid); } /** * Allocate a Flow ring buffer, * Init Ring buffer, send Msg to device about flow ring creation */ int dhd_bus_flow_ring_create_request(dhd_bus_t *bus, void *arg) { flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)arg; DHD_INFO(("%s :Flow create\n", __FUNCTION__)); /* Send Msg to device about flow ring creation */ if (dhd_prot_flow_ring_create(bus->dhd, flow_ring_node) != BCME_OK) return BCME_NOMEM; return BCME_OK; } /** Handle response from dongle on a 'flow ring create' request */ void dhd_bus_flow_ring_create_response(dhd_bus_t *bus, uint16 flowid, int32 status) { flow_ring_node_t *flow_ring_node; unsigned long flags; DHD_INFO(("%s :Flow Response %d \n", __FUNCTION__, flowid)); flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); ASSERT(flow_ring_node->flowid == flowid); if (status != BCME_OK) { DHD_ERROR(("%s Flow create Response failure error status = %d \n", __FUNCTION__, status)); /* Call Flow clean up */ dhd_bus_clean_flow_ring(bus, flow_ring_node); return; } DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); flow_ring_node->status = FLOW_RING_STATUS_OPEN; DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); /* Now add the Flow ring node into the active list * Note that this code to add the newly created node to the active * list was living in dhd_flowid_lookup. But note that after * adding the node to the active list the contents of node is being * filled in dhd_prot_flow_ring_create. * If there is a D2H interrupt after the node gets added to the * active list and before the node gets populated with values * from the Bottom half dhd_update_txflowrings would be called. * which will then try to walk through the active flow ring list, * pickup the nodes and operate on them. Now note that since * the function dhd_prot_flow_ring_create is not finished yet * the contents of flow_ring_node can still be NULL leading to * crashes. Hence the flow_ring_node should be added to the * active list only after its truely created, which is after * receiving the create response message from the Host. */ DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags); dll_prepend(&bus->const_flowring, &flow_ring_node->list); DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags); dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */ return; } int dhd_bus_flow_ring_delete_request(dhd_bus_t *bus, void *arg) { void * pkt; flow_queue_t *queue; flow_ring_node_t *flow_ring_node; unsigned long flags; DHD_INFO(("%s :Flow Delete\n", __FUNCTION__)); flow_ring_node = (flow_ring_node_t *)arg; DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); if (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) { DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); DHD_ERROR(("%s :Delete Pending Flow %d\n", __FUNCTION__, flow_ring_node->flowid)); return BCME_ERROR; } flow_ring_node->status = FLOW_RING_STATUS_DELETE_PENDING; queue = &flow_ring_node->queue; /* queue associated with flow ring */ #ifdef DHDTCPACK_SUPPRESS /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt, * when there is a newly coming packet from network stack. */ dhd_tcpack_info_tbl_clean(bus->dhd); #endif /* DHDTCPACK_SUPPRESS */ /* Flush all pending packets in the queue, if any */ while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { PKTFREE(bus->dhd->osh, pkt, TRUE); } ASSERT(DHD_FLOW_QUEUE_EMPTY(queue)); DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); /* Send Msg to device about flow ring deletion */ dhd_prot_flow_ring_delete(bus->dhd, flow_ring_node); return BCME_OK; } void dhd_bus_flow_ring_delete_response(dhd_bus_t *bus, uint16 flowid, uint32 status) { flow_ring_node_t *flow_ring_node; DHD_INFO(("%s :Flow Delete Response %d \n", __FUNCTION__, flowid)); flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); ASSERT(flow_ring_node->flowid == flowid); if (status != BCME_OK) { DHD_ERROR(("%s Flow Delete Response failure error status = %d \n", __FUNCTION__, status)); return; } /* Call Flow clean up */ dhd_bus_clean_flow_ring(bus, flow_ring_node); return; } /** This function is not called. Obsolete ? */ int dhd_bus_flow_ring_flush_request(dhd_bus_t *bus, void *arg) { void *pkt; flow_queue_t *queue; flow_ring_node_t *flow_ring_node; unsigned long flags; DHD_INFO(("%s :Flow Delete\n", __FUNCTION__)); flow_ring_node = (flow_ring_node_t *)arg; queue = &flow_ring_node->queue; /* queue associated with flow ring */ DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); #ifdef DHDTCPACK_SUPPRESS /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt, * when there is a newly coming packet from network stack. */ dhd_tcpack_info_tbl_clean(bus->dhd); #endif /* DHDTCPACK_SUPPRESS */ /* Flush all pending packets in the queue, if any */ while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { PKTFREE(bus->dhd->osh, pkt, TRUE); } ASSERT(DHD_FLOW_QUEUE_EMPTY(queue)); DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); /* Send Msg to device about flow ring flush */ dhd_prot_flow_ring_flush(bus->dhd, flow_ring_node); flow_ring_node->status = FLOW_RING_STATUS_FLUSH_PENDING; return BCME_OK; } void dhd_bus_flow_ring_flush_response(dhd_bus_t *bus, uint16 flowid, uint32 status) { flow_ring_node_t *flow_ring_node; if (status != BCME_OK) { DHD_ERROR(("%s Flow flush Response failure error status = %d \n", __FUNCTION__, status)); return; } flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); ASSERT(flow_ring_node->flowid == flowid); flow_ring_node->status = FLOW_RING_STATUS_OPEN; return; } uint32 dhd_bus_max_h2d_queues(struct dhd_bus *bus) { return bus->max_sub_queues; } /* To be symmetric with SDIO */ void dhd_bus_pktq_flush(dhd_pub_t *dhdp) { return; } void dhd_bus_set_linkdown(dhd_pub_t *dhdp, bool val) { dhdp->bus->is_linkdown = val; } int dhdpcie_bus_clock_start(struct dhd_bus *bus) { return dhdpcie_start_host_pcieclock(bus); } int dhdpcie_bus_clock_stop(struct dhd_bus *bus) { return dhdpcie_stop_host_pcieclock(bus); } int dhdpcie_bus_disable_device(struct dhd_bus *bus) { return dhdpcie_disable_device(bus); } int dhdpcie_bus_enable_device(struct dhd_bus *bus) { return dhdpcie_enable_device(bus); } int dhdpcie_bus_alloc_resource(struct dhd_bus *bus) { return dhdpcie_alloc_resource(bus); } void dhdpcie_bus_free_resource(struct dhd_bus *bus) { dhdpcie_free_resource(bus); } int dhd_bus_request_irq(struct dhd_bus *bus) { return dhdpcie_bus_request_irq(bus); } bool dhdpcie_bus_dongle_attach(struct dhd_bus *bus) { return dhdpcie_dongle_attach(bus); } int dhd_bus_release_dongle(struct dhd_bus *bus) { bool dongle_isolation; osl_t *osh; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); if (bus) { osh = bus->osh; ASSERT(osh); if (bus->dhd) { dongle_isolation = bus->dhd->dongle_isolation; dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE); } } return 0; } #ifdef BCMPCIE_OOB_HOST_WAKE int dhd_bus_oob_intr_register(dhd_pub_t *dhdp) { return dhdpcie_oob_intr_register(dhdp->bus); } void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp) { dhdpcie_oob_intr_unregister(dhdp->bus); } void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable) { dhdpcie_oob_intr_set(dhdp->bus, enable); } #endif /* BCMPCIE_OOB_HOST_WAKE */