148 lines
4.8 KiB
Plaintext
148 lines
4.8 KiB
Plaintext
NVIDIA Tegra SCE aux CPU, with communication via the "IVC" IPC protocol.
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SCE is an aux CPU which talks to CCPLEX over IVC.
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The SCE FW implements IVC, and uses HSP IRQs as part of IVC. The
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SCE FW expects AST regions 0/1/2 are already set up for the SCE to
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access FW in DRAM, SYSRAM if applicable, and the IVC memory.
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== SCE top-level node ==
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The SCE core is represented by the top-level node including direct HW resources
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such as clocks, resets etc.
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Required properties:
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- compatible: Should be "nvidia,tegra186-sce-ivc" for T18x.
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- reg: Address entries (SCE EVP, SCE PM. SCE CFG BASE, SCE CPU AST,
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SCE DMA AST)
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Formatted as per standard rules for this property.
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- reg-names: "sce-evp", "sce-pm", "sce-cfg", "ast-cpu", "ast-dma"
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as per the reg property.
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- clock-names: Names of the clocks required by SCE.
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Must include following entry:
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- sce-apb
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- clocks: Should contain an entry for each entry in clock-names.
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See ../clock/clock-bindings.txt for details.
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- reset-names: Names of the resets required for SCE.
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Must include following entries:
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- sce-apb
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- sce-nsysporeset
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- sce-nreset
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- sce-dbgresetn
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- sce-presetdbgn
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- sce-actmon
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- sce-pm
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- sce-dma
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- sce-hsp
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- tsctnsce
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- sce-tke
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- sce-gte
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- sce-cfg
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- resets: Should contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- nvidia,ivc-channels: List of IVC channel regions.
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For each IVC channel regions (usually, there is only one region):
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- an OF phandle pointing to the list,
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- the region number for Tegra AST,
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- the base address of the region in the remote processor (for address space
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translation),
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- the length of the region in bytes (must be a power of two).
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For IVC channel details, please refer to: ./tegra-ivc-channel.txt
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Optional properties:
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- nvidia,stream-id: should contain the SMMU Stream ID used.
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== SCE sub nodes ==
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* hsp
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Describes the hardware synchronization primitive(s) used between CCPLEX
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and SCE to signal incoming IVC messages or IVC write room.
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Required property:
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- compatible: Should match with the device driver implementing the
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cross-processor synchronization primitive.
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If the HSP doorbell is used for IVC notifications:
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- compatible: "nvidia,tegra186-hsp-doorbell"
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- nvidia,hsp-doorbell: <HSP-phandle HSP-ID HSP-DB>
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* HSP is a set of HW synchronization primitives used in Tegra to allow
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multiple processors to share resources and communicate together.
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* HSP-ID is NVIDIA Tegra HSP unique source ID for SCE, used in IPC.
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* HSP-DB is NVIDIA Tegra HSP unique doorbell number allotted to SCE.
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A HSP doorbell allows a set of source agents in Tegra to request the
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attention of specified target agent. In general the agents are processors
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and doorbell used as part of an IPC protocol.
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* For more HSP details, refer: ./tegra-hsp.txt.
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If the HSP shared mailbox is used for IVC notifications:
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- nvidia,hsp-shared-mailbox: <HSP-phandle MBOX-NUMBER HSP-phandle MBOX-NUMBER...>
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* HSP is a set of HW synchronization primitives used in Tegra to allow
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multiple processors to share resources and communicate together.
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* MBOX-NUMBER is number of shared mailbox pair
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* For more HSP details, refer: ../tegra-hsp.txt.
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- nvidia,hsp-shared-mailbox-names:
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Must include following entry:
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- ivc-pair
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If the HSP shared mailbox is used for boot synchronization:
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- nvidia,hsp-shared-mailbox: <HSP-phandle MBOX-NUMBER...>
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- nvidia,hsp-shared-mailbox-names:
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Must include following entry:
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- cmd-pair
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== Possible example ==
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tegra_sce: rtcpu@b000000 {
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compatible = "nvidia,tegra186-sce-ivc";
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nvidia,stream-id = <TEGRA_SID_RCE>;
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reg = <0 0xb000000 0 0x1000>,
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<0 0xb1f0000 0 0x40000>,
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<0 0xb230000 0 0x10000>,
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<0 0xb040000 0 0x10000>,
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<0 0xb050000 0 0x10000>;
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reg-names = "sce-evp", "sce-pm", "sce-cfg", "ast-cpu", "ast-dma";
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clocks = <&tegra_car TEGRA186_CLK_SCE_APB>;
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clock-names = "sce-apb";
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resets =
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<&tegra_car TEGRA186_RESET_SCE_APB>,
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<&tegra_car TEGRA186_RESET_SCE_NSYSPORESET>,
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<&tegra_car TEGRA186_RESET_SCE_NRESET>,
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<&tegra_car TEGRA186_RESET_SCE_DBGRESETN>,
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<&tegra_car TEGRA186_RESET_SCE_PRESETDBGN>,
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<&tegra_car TEGRA186_RESET_SCE_ACTMON>,
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<&tegra_car TEGRA186_RESET_SCE_PM>,
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<&tegra_car TEGRA186_RESET_SCE_DMA>,
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<&tegra_car TEGRA186_RESET_SCE_HSP>,
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<&tegra_car TEGRA186_RESET_TSCTNSCE>,
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<&tegra_car TEGRA186_RESET_SCE_TKE>,
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<&tegra_car TEGRA186_RESET_SCE_GTE>,
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<&tegra_car TEGRA186_RESET_SCE_CFG>;
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reset-names =
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"sce-apb",
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"sce-nsysporeset",
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"sce-nreset",
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"sce-dbgresetn",
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"sce-presetdbgn",
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"sce-actmon",
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"sce-pm",
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"sce-dma",
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"sce-hsp",
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"tsctnsce",
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"sce-tke",
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"sce-gte",
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"sce-cfg";
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nvidia,ivc-channels = <&tegra_camera_ivc 0x90000000 0x10000>;
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hsp {
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compatible = "nvidia,tegra186-hsp-mailbox";
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nvidia,hsp-shared-mailbox = <&sce_hsp 1 &sce_hsp 7>;
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nvidia,hsp-shared-mailbox-names = "ivc-pair", "cmd-pair";
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};
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};
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