73 lines
2.9 KiB
Plaintext
73 lines
2.9 KiB
Plaintext
* NVIDIA Tegra, Universal Flash Storage (UFS) Host Controller
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UFSHC nodes are defined to describe on-chip UFS host controllers.
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Each UFS controller instance should have its own node.
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Required properties:
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- compatible : compatible list, contains "jedec,ufs-1.1"
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- interrupts : <interrupt mapping for UFS host controller IRQ>
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- reg : <registers mapping>
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Optional properties:
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property.
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- freq-table-hz : Array of <min max> operating frequencies stored in the same
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order as the clocks property. If this property is not
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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- nvidia,configure-uphy-pll3 : Provides an option to configure uphy_pll3 for
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ufs rate_a and rate_b modes.
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- nvidia,enable-scramble : Enables scramble functionality.
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It is required to enable scramble functionality, which is used for
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encryption.
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- nvidia,enable-rx-calib : Enables rx calibration functionality.
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It is required for UFS High Speed modes.
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- nvidia,enable-x2-config : Enables 2 lane register programming support.
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Should be enabled if 2 lanes are dedicated to UFS.
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- nvidia,enable-hs-mode : Flag to enable UFS High Speed modes. If this flag is not set
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UFS will be enumerated in PWM mode.
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- nvidia,mask-fast-auto-mode : Flag to disable fast auto mode.
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When enabled UFS Fast auto mode will not be supported and
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fast mode will be supported.
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- nvidia,mask-hs-mode-b : Flag to disable hs_rate_b series.
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When enabled UFS hs_rate_b series will not be supported and
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hs_rate_a series will be supported.
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- nvidia,enable-hibern8-war : Flag to enable hibernate war.
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when enabled, ufs tegra driver will enable a WAR to reset Mphy.
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- nvidia,max-hs-gear : Flag to set Max UFS HS Gear. Values are defined as below.
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UFS_HS_G1 = <1>;
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UFS_HS_G2 = <2>;
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UFS_HS_G3 = <3>;
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- nvidia,max-pwm-gear : Flag to set Max UFS PWM Gear. Values are defined as below.
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UFS_PWM_G1 = <1>;
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UFS_PWM_G2 = <2>;
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UFS_PWM_G3 = <3>;
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UFS_PWM_G4 = <4>;
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UFS_PWM_G5 = <5>;
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UFS_PWM_G6 = <6>;
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UFS_PWM_G7 = <7>;
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Note: If above properties are not defined it can be assumed that the supply
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regulators or clocks are always on.
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Example:
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ufshc@0xfc598000 {
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compatible = "jedec,ufs-1.1";
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reg = <0xfc598000 0x800>;
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interrupts = <0 28 0>;
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clocks = <&core 0>, <&ref 0>, <&iface 0>;
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clock-names = "core_clk", "ref_clk", "iface_clk";
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freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
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nvidia,enable-x2-config;
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nvidia,enable-rx-calib;
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nvidia,enable-hs-mode;
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nvidia,mask-fast-auto-mode;
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nvidia,max-hs-gear = <3>;
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nvidia,max-pwm-gear = <4>;
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};
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