149 lines
4.4 KiB
C
149 lines
4.4 KiB
C
/*
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* drivers/misc/tegra-profiler/armv8_events.h
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef __ARMV8_EVENTS_H
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#define __ARMV8_EVENTS_H
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#define QUADD_AA64_PMUVER_PMUV3 0x01
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#define QUADD_AA64_PMUVER_PMUV3_EVCNT16 0x04
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#define QUADD_AA64_CPU_IMP_NVIDIA 'N'
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#define QUADD_AA64_CPU_IDCODE_CORTEX_A57 0x01
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#define QUADD_AA64_CPU_IDCODE_CORTEX_A53 0x03
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#define QUADD_AA64_ID_AA64DFR0_PMUVER_MASK 0x0f
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enum {
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QUADD_AA64_CPU_TYPE_UNKNOWN = 1,
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QUADD_AA64_CPU_TYPE_UNKNOWN_IMP,
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QUADD_AA64_CPU_TYPE_ARM,
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QUADD_AA64_CPU_TYPE_CORTEX_A53,
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QUADD_AA64_CPU_TYPE_CORTEX_A57,
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QUADD_AA64_CPU_TYPE_DENVER,
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};
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/*
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* Performance Monitors Control Register
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*/
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/* All counters, including PMCCNTR_EL0, are disabled/enabled */
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#define QUADD_ARMV8_PMCR_E (1 << 0)
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/* Reset all event counters, not including PMCCNTR_EL0, to 0 */
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#define QUADD_ARMV8_PMCR_P (1 << 1)
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/* Reset PMCCNTR_EL0 to 0 */
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#define QUADD_ARMV8_PMCR_C (1 << 2)
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/* Clock divider: PMCCNTR_EL0 counts every clock cycle/every 64 clock cycles */
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#define QUADD_ARMV8_PMCR_D (1 << 3)
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/* Export of events is disabled/enabled */
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#define QUADD_ARMV8_PMCR_X (1 << 4)
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/* Disable cycle counter, PMCCNTR_EL0 when event counting is prohibited */
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#define QUADD_ARMV8_PMCR_DP (1 << 5)
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/* Long cycle count enable */
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#define QUADD_ARMV8_PMCR_LC (1 << 6)
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/* Number of event counters */
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#define QUADD_ARMV8_PMCR_N_SHIFT 11
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#define QUADD_ARMV8_PMCR_N_MASK 0x1f
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/* Identification code */
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#define QUADD_ARMV8_PMCR_IDCODE_SHIFT 16
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#define QUADD_ARMV8_PMCR_IDCODE_MASK 0xff
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/* Implementer code */
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#define QUADD_ARMV8_PMCR_IMP_SHIFT 24
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/* Mask for writable bits */
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#define QUADD_ARMV8_PMCR_WR_MASK 0x3f
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/* Cycle counter */
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#define QUADD_ARMV8_CCNT_BIT 31
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#define QUADD_ARMV8_CCNT (1 << QUADD_ARMV8_CCNT_BIT)
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/*
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* Performance Counter Selection Register mask
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*/
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#define QUADD_ARMV8_SELECT_MASK 0x1f
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/*
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* EVTSEL Register mask
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*/
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#define QUADD_ARMV8_EVTSEL_MASK 0xff
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#define QUADD_ARMV8_COUNTERS_MASK_PMUV3 0x3f
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#define QUADD_ARMV8_PMU_NVEXT_SHIFT 4
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#define QUADD_ARMV8_PMU_NVEXT_MASK 0x0f
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/*
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* ARMv8 PMUv3 Performance Events handling code.
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* Common event types.
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*/
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enum {
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/* Required events. */
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QUADD_ARMV8_HW_EVENT_PMNC_SW_INCR = 0x00,
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QUADD_ARMV8_HW_EVENT_L1_DCACHE_REFILL = 0x03,
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QUADD_ARMV8_HW_EVENT_L1_DCACHE_ACCESS = 0x04,
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QUADD_ARMV8_HW_EVENT_PC_BRANCH_MIS_PRED = 0x10,
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QUADD_ARMV8_HW_EVENT_CLOCK_CYCLES = 0x11,
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QUADD_ARMV8_HW_EVENT_PC_BRANCH_PRED = 0x12,
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/* At least one of the following is required. */
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QUADD_ARMV8_HW_EVENT_INSTR_EXECUTED = 0x08,
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QUADD_ARMV8_HW_EVENT_OP_SPEC = 0x1B,
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/* Common architectural events. */
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QUADD_ARMV8_HW_EVENT_MEM_READ = 0x06,
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QUADD_ARMV8_HW_EVENT_MEM_WRITE = 0x07,
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QUADD_ARMV8_HW_EVENT_EXC_TAKEN = 0x09,
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QUADD_ARMV8_HW_EVENT_EXC_EXECUTED = 0x0A,
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QUADD_ARMV8_HW_EVENT_CID_WRITE = 0x0B,
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QUADD_ARMV8_HW_EVENT_PC_WRITE = 0x0C,
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QUADD_ARMV8_HW_EVENT_PC_IMM_BRANCH = 0x0D,
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QUADD_ARMV8_HW_EVENT_PC_PROC_RETURN = 0x0E,
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QUADD_ARMV8_HW_EVENT_MEM_UNALIGNED_ACCESS = 0x0F,
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QUADD_ARMV8_HW_EVENT_TTBR_WRITE = 0x1C,
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/* Common microarchitectural events. */
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QUADD_ARMV8_HW_EVENT_L1_ICACHE_REFILL = 0x01,
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QUADD_ARMV8_HW_EVENT_ITLB_REFILL = 0x02,
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QUADD_ARMV8_HW_EVENT_DTLB_REFILL = 0x05,
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QUADD_ARMV8_HW_EVENT_MEM_ACCESS = 0x13,
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QUADD_ARMV8_HW_EVENT_L1_ICACHE_ACCESS = 0x14,
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QUADD_ARMV8_HW_EVENT_L1_DCACHE_WB = 0x15,
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QUADD_ARMV8_HW_EVENT_L2_CACHE_ACCESS = 0x16,
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QUADD_ARMV8_HW_EVENT_L2_CACHE_REFILL = 0x17,
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QUADD_ARMV8_HW_EVENT_L2_CACHE_WB = 0x18,
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QUADD_ARMV8_HW_EVENT_BUS_ACCESS = 0x19,
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QUADD_ARMV8_HW_EVENT_MEM_ERROR = 0x1A,
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QUADD_ARMV8_HW_EVENT_BUS_CYCLES = 0x1D,
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};
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/*
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* ARMv8 Cortex-A57 specific event types.
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*/
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enum {
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QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_LD = 0x42,
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QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_ST = 0x43,
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QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_LD = 0x52,
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QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_ST = 0x53,
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};
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#define QUADD_ARMV8_UNSUPPORTED_EVENT 0xff00
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#define QUADD_ARMV8_CPU_CYCLE_EVENT 0xffff
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#endif /* __ARMV8_EVENTS_H */
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