683 lines
17 KiB
C
683 lines
17 KiB
C
/*
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*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/debugfs.h>
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#include <linux/of.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_qos.h>
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#include <linux/thermal.h>
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#include <dt-bindings/thermal/nvidia,tegra-thermal-throttle.h>
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#define KHZ_TO_HZ 1000
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#define CPU_STEP_HZ (76800 * KHZ_TO_HZ)
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#define GPU_STEP_HZ (102 * KHZ_TO_HZ * KHZ_TO_HZ)
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#define MAX_CPU_CLUSTERS 4
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struct tegra_throt_cdev_clk;
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struct tegra_throt_cdev {
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struct thermal_cooling_device *cdev;
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struct tegra_throt_cdev_clk *clks;
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struct list_head cdev_list;
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char cdev_type[64];
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int num_clks;
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int max_state;
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int cur_state;
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int cutoff;
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};
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struct tegra_throt_clk {
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struct clk *clk;
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unsigned long max_rate;
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unsigned long min_rate;
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unsigned long throt_rate;
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unsigned long step_hz;
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struct list_head cdev_clk_list;
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int type;
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int steps;
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char *name;
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char **clk_names;
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int num_clk_handles;
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};
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struct tegra_throt_cdev_clk {
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struct tegra_throt_clk *throt_clk;
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struct tegra_throt_cdev *throt_cdev;
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struct list_head clk_list;
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int offset_hz;
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int slope_adj;
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unsigned long cdev_throt_rate;
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};
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static struct pm_qos_request tegra_throt_gpu_req;
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static int tegra_throt_cpu_req;
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static LIST_HEAD(tegra_throt_cdev_list);
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static DEFINE_MUTEX(tegra_throt_lock);
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static struct dentry *tegra_throt_root;
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static unsigned long cpu_max_freq;
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static unsigned long cpu_min_freq;
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static char *cpu_clks[MAX_CPU_CLUSTERS] = { "cpu0", "cpu1", "cpu2", "cpu3" };
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static char *gpu_clks[] = { "gpu" };
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static struct tegra_throt_clk throt_clks[TEGRA_THROTTLE_MAX] = {
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{
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.name = "cpu",
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.clk_names = cpu_clks,
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.step_hz = CPU_STEP_HZ,
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.type = TEGRA_THROTTLE_CPU,
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.num_clk_handles = MAX_CPU_CLUSTERS,
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},
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{
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.name = "gpu",
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.clk_names = gpu_clks,
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.step_hz = GPU_STEP_HZ,
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.type = TEGRA_THROTTLE_GPU,
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.num_clk_handles = 1,
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},
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};
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static const struct of_device_id tegra_throt_of_match[] = {
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{
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.compatible = "nvidia,tegra-thermal-throttle",
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.data = &throt_clks,
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},
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{ },
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};
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static unsigned long tegra_throt_calc_rate(unsigned long idx,
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unsigned long maxf, unsigned long minf,
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unsigned long step, unsigned long offset,
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int slope_adj)
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{
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unsigned long throt_rate, throt_amt;
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throt_amt = ((idx * step * 100) / slope_adj);
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throt_amt = (throt_amt > offset) ? (throt_amt - offset) : 0;
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throt_rate = (throt_amt > maxf) ? minf : (maxf - throt_amt);
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throt_rate = max(minf, min(throt_rate, maxf));
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return throt_rate;
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}
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static int tegra_throt_cpufreq_notifier(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct cpufreq_policy *policy = data;
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if (event != CPUFREQ_ADJUST)
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return 0;
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if (policy->max > tegra_throt_cpu_req)
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cpufreq_verify_within_limits(policy, 0, tegra_throt_cpu_req);
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return 0;
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}
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static struct notifier_block tegra_throt_cpufreq_nb = {
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.notifier_call = tegra_throt_cpufreq_notifier,
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};
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static struct tegra_throt_clk *tegra_throt_find_clk(
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struct tegra_throt_clk *pclks, int type)
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{
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int i;
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for (i = 0; i < TEGRA_THROTTLE_MAX; i++)
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if (pclks[i].type == type)
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break;
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if (!IS_ERR(pclks[i].clk))
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return &pclks[i];
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return NULL;
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}
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static void tegra_throt_rate_set(int type, unsigned long rate)
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{
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int cpu;
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rate /= KHZ_TO_HZ;
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switch (type) {
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case TEGRA_THROTTLE_CPU:
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for_each_present_cpu(cpu) {
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tegra_throt_cpu_req = rate;
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cpufreq_update_policy(cpu);
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}
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break;
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case TEGRA_THROTTLE_GPU:
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pm_qos_update_request(&tegra_throt_gpu_req, rate);
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break;
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default:
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pr_err("tegra_throt: incorrect type: %d\n", type);
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break;
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}
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}
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static int tegra_throt_set_cur_state(struct thermal_cooling_device *cdev,
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unsigned long cur_state)
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{
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int i;
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struct tegra_throt_cdev *tcd = (struct tegra_throt_cdev *)cdev->devdata;
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tcd->cur_state = cur_state;
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for (i = 0; i < tcd->num_clks; i++) {
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unsigned long throt_rate = UINT_MAX;
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struct tegra_throt_cdev_clk *pos, *tcc = &tcd->clks[i];
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struct tegra_throt_clk *tclk = tcc->throt_clk;
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tcc->cdev_throt_rate = tegra_throt_calc_rate(cur_state,
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tclk->max_rate, tclk->min_rate,
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tclk->step_hz, tcc->offset_hz,
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tcc->slope_adj);
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list_for_each_entry(pos, &tclk->cdev_clk_list, clk_list)
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throt_rate = min(throt_rate, pos->cdev_throt_rate);
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/*
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* Thermal framework takes only per cdev lock before calling
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* here. Need to protect throt_rate which is per clock.
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*/
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mutex_lock(&tegra_throt_lock);
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if (throt_rate != tclk->throt_rate) {
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tegra_throt_rate_set(tclk->type, throt_rate);
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tclk->throt_rate = throt_rate;
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dev_dbg(&cdev->device, "type:%d throt_rate: %ldKHz\n",
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tclk->type, throt_rate/KHZ_TO_HZ);
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}
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mutex_unlock(&tegra_throt_lock);
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}
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return 0;
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}
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static int tegra_throt_get_cur_state(struct thermal_cooling_device *cdev,
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unsigned long *cur_state)
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{
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struct tegra_throt_cdev *tcd = (struct tegra_throt_cdev *)cdev->devdata;
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*cur_state = tcd->cur_state;
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return 0;
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}
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static int tegra_throt_get_max_state(struct thermal_cooling_device *cdev,
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unsigned long *max_state)
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{
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struct tegra_throt_cdev *tcd = (struct tegra_throt_cdev *)cdev->devdata;
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*max_state = tcd->max_state;
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return 0;
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}
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static const struct thermal_cooling_device_ops tegra_throt_ops = {
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.get_max_state = tegra_throt_get_max_state,
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.get_cur_state = tegra_throt_get_cur_state,
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.set_cur_state = tegra_throt_set_cur_state,
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};
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static int tegra_throt_calc_max_state(struct tegra_throt_cdev *tcd)
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{
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int i, steps, max_state = 0;
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for (i = 0; i < tcd->num_clks; i++) {
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struct tegra_throt_cdev_clk *tcc = &tcd->clks[i];
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steps = (((tcc->offset_hz / tcc->throt_clk->step_hz) +
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tcc->throt_clk->steps) * tcc->slope_adj) / 100;
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if (tcd->cutoff)
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max_state = (max_state) ? min(steps, max_state) : steps;
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else
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max_state = max(steps, max_state);
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}
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return max_state;
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}
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#ifdef CONFIG_DEBUG_FS
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static int cdev_freq_table_show(struct seq_file *s, void *data)
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{
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int i, j;
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unsigned long throt_rate;
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struct tegra_throt_cdev *tcd = s->private;
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struct tegra_throt_cdev_clk *tcc;
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for (i = 0; i <= tcd->max_state; i++) {
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for (j = 0; j < tcd->num_clks; j++) {
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tcc = &tcd->clks[j];
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throt_rate = tegra_throt_calc_rate(i,
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tcc->throt_clk->max_rate,
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tcc->throt_clk->min_rate,
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tcc->throt_clk->step_hz, tcc->offset_hz,
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tcc->slope_adj);
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seq_printf(s, " %7lu", throt_rate);
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}
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seq_puts(s, "\n");
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}
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return 0;
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}
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static int table_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cdev_freq_table_show, inode->i_private);
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}
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static const struct file_operations ftable_fops = {
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.open = table_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int prop_get(void *data, u64 *val)
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{
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*val = *((int *)data);
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return 0;
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}
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static int cutoff_set(void *data, u64 val)
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{
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int *prop = (int *)data;
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struct tegra_throt_cdev *tcd = container_of(prop,
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struct tegra_throt_cdev, cutoff);
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*prop = (int)val;
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tcd->max_state = tegra_throt_calc_max_state(tcd);
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return 0;
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}
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static int offset_set(void *data, u64 val)
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{
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int *prop = (int *)data;
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struct tegra_throt_cdev_clk *tcc = container_of(prop,
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struct tegra_throt_cdev_clk,
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offset_hz);
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*prop = val;
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tcc->throt_cdev->max_state = tegra_throt_calc_max_state(
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tcc->throt_cdev);
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return 0;
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}
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static int slope_set(void *data, u64 val)
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{
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int *prop = (int *)data;
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struct tegra_throt_cdev_clk *tcc = container_of(prop,
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struct tegra_throt_cdev_clk,
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slope_adj);
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*prop = val;
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tcc->throt_cdev->max_state = tegra_throt_calc_max_state(
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tcc->throt_cdev);
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(cfops, prop_get, cutoff_set, "%lld\n");
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DEFINE_SIMPLE_ATTRIBUTE(ofops, prop_get, offset_set, "%lld\n");
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DEFINE_SIMPLE_ATTRIBUTE(sfops, prop_get, slope_set, "%lld\n");
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DEFINE_SIMPLE_ATTRIBUTE(tfops, prop_get, NULL, "%lld\n");
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static void tegra_throt_dbgfs_remove(struct dentry *root)
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{
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debugfs_remove_recursive(root);
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}
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static int tegra_throt_dbgfs_create(struct dentry **root)
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{
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*root = debugfs_create_dir("tegra_throttle", NULL);
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return (!root) ? -ENODEV : 0;
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}
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static void tegra_throt_dbgfs_init(struct platform_device *pdev,
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struct tegra_throt_cdev *tcd, struct dentry *throt_root)
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{
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int i;
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struct dentry *r, *cr, *f;
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if (!tcd)
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goto err;
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r = debugfs_create_dir(tcd->cdev_type, throt_root);
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f = r ? debugfs_create_file("cutoff", 0644, r, &tcd->cutoff, &cfops) :
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r;
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f = f ? debugfs_create_file("table", 0644, r, tcd, &ftable_fops) : f;
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if (!f)
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goto err;
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for (i = 0; i < tcd->num_clks; i++) {
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struct tegra_throt_cdev_clk *tcc = &tcd->clks[i];
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cr = debugfs_create_dir(tcc->throt_clk->name, r);
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if (!cr)
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goto err;
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f = debugfs_create_file("offset", 0644, cr, &tcc->offset_hz,
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&ofops);
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f = f ? debugfs_create_file("slope-adj", 0644, cr,
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&tcc->slope_adj, &sfops) : f;
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f = f ? debugfs_create_file("throt-rate", 0644, cr,
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&tcc->cdev_throt_rate, &tfops) : f;
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if (!f)
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goto err;
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}
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return;
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err:
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dev_err(&pdev->dev, "failed to initialize debugfs\n");
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}
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#else /* CONFIG_DEBUG_FS */
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static void tegra_throt_dbgfs_init(struct platform_device *pdev,
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struct tegra_throt_cdev *tcd, struct dentry *root)
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{}
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static void tegra_throt_dbgfs_remove(struct dentry *root)
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{}
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static int tegra_throt_dbgfs_create(struct dentry **root)
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{
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return 0;
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}
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#endif
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static int tegra_throt_cdev_clk_init(struct platform_device *pdev,
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struct tegra_throt_clk *pclks, struct device_node *np,
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struct tegra_throt_cdev *tcd)
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{
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int i, j, ret = 0, n;
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u32 prop[3 * TEGRA_THROTTLE_MAX];
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struct tegra_throt_cdev_clk *tcc;
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struct tegra_throt_clk *tclk;
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n = of_property_count_u32_elems(np, "nvidia,throttle-clocks");
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if (n <= 0)
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return -ENODEV;
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if ((n % 3) != 0)
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return -EINVAL;
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ret = of_property_read_u32_array(np, "nvidia,throttle-clocks", prop, n);
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if (ret)
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return -EINVAL;
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tcd->num_clks = n / 3;
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tcd->clks = devm_kzalloc(&pdev->dev,
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(tcd->num_clks * sizeof(struct tegra_throt_cdev_clk)),
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GFP_KERNEL);
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if (IS_ERR_OR_NULL(tcd->clks))
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return -ENOMEM;
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for (i = 0, j = 0; j < tcd->num_clks; i = i + 3, j++) {
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tcc = &tcd->clks[j];
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tclk = tegra_throt_find_clk(pclks, prop[i]);
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if (!tclk)
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return -ENODEV;
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tcc->throt_clk = tclk;
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tcc->slope_adj = prop[i+1];
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if (!tcc->slope_adj)
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return -EINVAL;
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tcc->offset_hz = prop[i+2];
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dev_info(&pdev->dev, "cdev:%s clk:%d:%s off:%d slope-adj:%d\n",
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tcd->cdev_type, tcc->throt_clk->type,
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tcc->throt_clk->name, tcc->offset_hz,
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tcc->slope_adj);
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tcc->cdev_throt_rate = UINT_MAX;
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tcc->throt_cdev = tcd;
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list_add(&tcc->clk_list, &tclk->cdev_clk_list);
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}
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return 0;
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}
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static int tegra_throt_cdev_init(struct platform_device *pdev,
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struct tegra_throt_clk *pclks)
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{
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const char *str;
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int val, cnt = 0;
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struct device_node *np = pdev->dev.of_node;
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struct device_node *ch;
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struct tegra_throt_cdev *tcd = NULL;
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if (!np)
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return -ENODEV;
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if (tegra_throt_dbgfs_create(&tegra_throt_root))
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return -ENODEV;
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for_each_child_of_node(np, ch) {
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if (!of_device_is_available(ch))
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continue;
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if (of_property_read_string(ch, "cdev-type", &str))
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continue;
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tcd = devm_kzalloc(&pdev->dev, sizeof(struct tegra_throt_cdev),
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GFP_KERNEL);
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if (IS_ERR_OR_NULL(tcd))
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return -ENOMEM;
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strlcpy(tcd->cdev_type, str, sizeof(tcd->cdev_type));
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val = tegra_throt_cdev_clk_init(pdev, pclks, ch, tcd);
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if (val) {
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dev_err(&pdev->dev, "cdev:%s clk init failed: %0x0x\n",
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tcd->cdev_type, val);
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devm_kfree(&pdev->dev, tcd);
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continue;
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}
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if (!of_property_read_u32(ch, "nvidia,cutoff", &val))
|
|
tcd->cutoff = (val) ? 1 : 0;
|
|
|
|
tcd->max_state = tegra_throt_calc_max_state(tcd);
|
|
tcd->cdev = thermal_of_cooling_device_register(ch,
|
|
tcd->cdev_type, tcd, &tegra_throt_ops);
|
|
if (IS_ERR(tcd->cdev)) {
|
|
devm_kfree(&pdev->dev, tcd);
|
|
continue;
|
|
}
|
|
|
|
cnt++;
|
|
list_add(&tcd->cdev_list, &tegra_throt_cdev_list);
|
|
dev_info(&pdev->dev, "cdev:%s max_state:%d cutoff:%d\n",
|
|
tcd->cdev_type, tcd->max_state, tcd->cutoff);
|
|
tegra_throt_dbgfs_init(pdev, tcd, tegra_throt_root);
|
|
}
|
|
|
|
if (!cnt)
|
|
dev_err(&pdev->dev, "Missing cooling devices\n");
|
|
|
|
return (cnt) ? 0 : -ENODEV;
|
|
}
|
|
|
|
static int tegra_throt_freq_gov_init(int type)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
switch (type) {
|
|
case TEGRA_THROTTLE_CPU:
|
|
tegra_throt_cpu_req = UINT_MAX;
|
|
ret = cpufreq_register_notifier(&tegra_throt_cpufreq_nb,
|
|
CPUFREQ_POLICY_NOTIFIER);
|
|
if (ret)
|
|
pr_info("tegra_throt: missing cpufreq: 0x%x\n", ret);
|
|
|
|
break;
|
|
case TEGRA_THROTTLE_GPU:
|
|
pm_qos_add_request(&tegra_throt_gpu_req, PM_QOS_GPU_FREQ_MAX,
|
|
PM_QOS_GPU_FREQ_MAX_DEFAULT_VALUE);
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_throt_clk_get(struct platform_device *pdev,
|
|
struct tegra_throt_clk *pclk)
|
|
{
|
|
int i;
|
|
int ret = -EINVAL;
|
|
|
|
for (i = 0; i < pclk->num_clk_handles; i++) {
|
|
if (!strncmp(pclk->clk_names[i], "cpu", 3)) {
|
|
/* non CCF controlled clock */
|
|
pclk->max_rate = cpu_max_freq * KHZ_TO_HZ;
|
|
pclk->min_rate = cpu_min_freq * KHZ_TO_HZ;
|
|
ret = 0;
|
|
} else {
|
|
/* CCF controlled clock */
|
|
pclk->clk = devm_clk_get(&pdev->dev,
|
|
pclk->clk_names[i]);
|
|
if (!IS_ERR(pclk->clk)) {
|
|
pclk->max_rate = clk_round_rate(pclk->clk,
|
|
UINT_MAX);
|
|
pclk->min_rate = clk_round_rate(pclk->clk, 0);
|
|
ret = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ret)
|
|
dev_err(&pdev->dev, "failed to get clk:%s\n", pclk[i].name);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_throt_clk_init(struct platform_device *pdev,
|
|
struct tegra_throt_clk *pclks)
|
|
{
|
|
int i, ret = -ENODEV;
|
|
|
|
for (i = 0; i < TEGRA_THROTTLE_MAX; i++) {
|
|
ret = tegra_throt_freq_gov_init(pclks[i].type);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Missing frequency governors\n");
|
|
continue;
|
|
}
|
|
|
|
if (tegra_throt_clk_get(pdev, &pclks[i]) != 0)
|
|
continue;
|
|
|
|
INIT_LIST_HEAD(&pclks[i].cdev_clk_list);
|
|
pclks[i].steps = DIV_ROUND_UP((pclks[i].max_rate -
|
|
pclks[i].min_rate), pclks[i].step_hz);
|
|
pclks[i].throt_rate = UINT_MAX;
|
|
dev_info(&pdev->dev, "clk:%s max:%ld, min:%ld steps:%d\n",
|
|
pclks[i].name, pclks[i].max_rate,
|
|
pclks[i].min_rate, pclks[i].steps);
|
|
ret = 0;
|
|
}
|
|
|
|
if (ret)
|
|
dev_err(&pdev->dev, "missing clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_throt_cpu_min_max(void)
|
|
{
|
|
struct cpufreq_policy policy;
|
|
int cpu;
|
|
int cnt = 0;
|
|
|
|
cpu_max_freq = 0;
|
|
cpu_min_freq = UINT_MAX;
|
|
/* In cases when cpufreq_single_policy is not set, the per cpu max/min
|
|
* could differ. In such cases, choose the highest max frequency and
|
|
* lowest min frequency to cover all frequency points. Throttling slope
|
|
* could be increased if this is deemed too slow.
|
|
*/
|
|
for_each_online_cpu(cpu) {
|
|
if (!cpufreq_get_policy(&policy, cpu)) {
|
|
if (policy.cpuinfo.max_freq > cpu_max_freq)
|
|
cpu_max_freq = policy.cpuinfo.max_freq;
|
|
if (policy.cpuinfo.min_freq < cpu_min_freq)
|
|
cpu_min_freq = policy.cpuinfo.min_freq;
|
|
cnt++;
|
|
}
|
|
}
|
|
|
|
/* continue with probe as long as one cpu is online */
|
|
return (cnt) ? 0 : -ENODEV;
|
|
}
|
|
|
|
static int tegra_throt_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_throt_cdev *pos;
|
|
|
|
dev_info(&pdev->dev, "remove\n");
|
|
cpufreq_unregister_notifier(&tegra_throt_cpufreq_nb,
|
|
CPUFREQ_POLICY_NOTIFIER);
|
|
pm_qos_remove_request(&tegra_throt_gpu_req);
|
|
tegra_throt_dbgfs_remove(tegra_throt_root);
|
|
list_for_each_entry(pos, &tegra_throt_cdev_list, cdev_list)
|
|
thermal_cooling_device_unregister(pos->cdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_throt_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
const struct of_device_id *match;
|
|
struct tegra_throt_clk *pclks;
|
|
|
|
ret = tegra_throt_cpu_min_max();
|
|
if (ret != 0) {
|
|
dev_info(&pdev->dev, "cpufreq policy is not ready defer\n");
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
match = of_match_node(tegra_throt_of_match, pdev->dev.of_node);
|
|
if (!match)
|
|
return -ENODEV;
|
|
|
|
pclks = (struct tegra_throt_clk *)match->data;
|
|
if (!pclks)
|
|
return -EINVAL;
|
|
|
|
ret = tegra_throt_clk_init(pdev, pclks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tegra_throt_cdev_init(pdev, pclks);
|
|
if (ret)
|
|
tegra_throt_remove(pdev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver tegra_throttle_driver = {
|
|
.driver = {
|
|
.name = "tegra-thermal-throttle",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra_throt_of_match,
|
|
},
|
|
.probe = tegra_throt_probe,
|
|
.remove = tegra_throt_remove,
|
|
};
|
|
|
|
module_platform_driver(tegra_throttle_driver);
|
|
MODULE_AUTHOR("Srikar Srimath Tirumala <srikars@nvidia.com>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra Clock Thermal Throttle Driver");
|
|
MODULE_LICENSE("GPL v2");
|