80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* sn65dsi86_dsi2edp.h: dsi to edp controller sn65dsi86 driver.
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*
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* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Bibek Basu <bbasu@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_SN65DSI86_DSI2EDP_H
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#define __DRIVERS_VIDEO_TEGRA_DC_SN65DSI86_DSI2EDP_H
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struct tegra_dc_dsi2edp_data {
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struct tegra_dc_dsi_data *dsi;
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struct i2c_client *client_i2c;
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struct regmap *regmap;
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struct tegra_dc_mode *mode;
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bool dsi2edp_enabled;
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struct mutex lock;
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struct {
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int en_gpio; /* GPIO */
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int en_gpio_flags;
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int pll_refclk_cfg; /* reg.0x0a */
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int dp_ssc_cfg; /* reg.0x93 */
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int negative_hsync;
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int negative_vsync;
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int disable_assr;
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int enable_colorbar;
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} init;
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};
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#define SN65DSI86_DEVICE_ID 0x00
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#define SN65DSI86_DEVICE_REV 0x08
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#define SN65DSI86_SOFT_RESET 0X09
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#define SN65DSI86_PLL_REFCLK_CFG 0x0A
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#define SN65DSI86_PLL_EN 0x0D
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#define SN65DSI86_DSI_CFG1 0x10
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#define SN65DSI86_DSI_CFG2 0x11
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#define SN65DSI86_DSI_CHA_CLK_RANGE 0x12
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#define SN65DSI86_DSI_CHB_CLK_RANGE 0x13
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#define SN65DSI86_VIDEO_CHA_LINE_LOW 0x20
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#define SN65DSI86_VIDEO_CHA_LINE_HIGH 0x21
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#define SN65DSI86_VIDEO_CHB_LINE_LOW 0x22
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#define SN65DSI86_VIDEO_CHB_LINE_HIGH 0x23
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#define SN65DSI86_CHA_VERT_DISP_SIZE_LOW 0x24
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#define SN65DSI86_CHA_VERT_DISP_SIZE_HIGH 0x25
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#define SN65DSI86_CHA_HSYNC_PULSE_WIDTH_LOW 0x2C
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#define SN65DSI86_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2D
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#define SN65DSI86_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
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#define SN65DSI86_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
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#define SN65DSI86_CHA_HORIZONTAL_BACK_PORCH 0x34
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#define SN65DSI86_CHA_VERTICAL_BACK_PORCH 0x36
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#define SN65DSI86_CHA_HORIZONTAL_FRONT_PORCH 0x38
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#define SN65DSI86_CHA_VERTICAL_FRONT_PORCH 0x3a
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#define SN65DSI86_COLOR_BAR_CFG 0x3c
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#define SN65DSI86_FRAMING_CFG 0x5a
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#define SN65DSI86_DP_18BPP_EN 0x5b
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#define SN65DSI86_REG_0x5c 0x5c
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#define SN65DSI86_GPIO_CTRL_CFG 0x5f
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#define SN65DSI86_DP_SSC_CFG 0x93
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#define SN65DSI86_DP_CFG 0x94
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#define SN65DSI86_TRAINING_CFG 0x95
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#define SN65DSI86_ML_TX_MODE 0x96
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#define RETRY_PLL 45 /* 2mSec */
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#define RETRY_HPD 25 /* 5mSec */
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#define RETRY_LT 300 /* 5mSec */
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#endif
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